OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

MC74HC160ADR2G

P1-P3P4-P6P7-P9P10-P12
MC74HC160A
http://onsemi.com
4
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input t
r
= t
f
= 6 ns)
Symbol
Parameter
V
CC
V
Guaranteed Limit
Unit
− 55 to
25°C
v 85°C v 125°C
f
max
Maximum Clock Frequency (50% Duty Cycle)*
(Figures 3 and 8)
2.0
4.5
6.0
6.0
30
35
4.8
24
28
4.0
20
24
MHz
t
PLH
Maximum Propagation Delay, Clock to Q
(Figures 3 and 8)
2.0
4.5
6.0
170
34
29
215
43
37
255
51
43
ns
t
PHL
2.0
4.5
6.0
205
41
35
255
51
43
310
62
53
t
PHL
Maximum Propagation Delay, Reset to Q (HC160A Only)
(Figures 4 and 8)
2.0
4.5
6.0
210
42
36
265
53
45
315
63
54
ns
t
PLH
Maximum Propagation Delay, Enable T to Ripple Carry Out
(Figures 5 and 8)
2.0
4.5
6.0
160
32
27
200
40
34
240
48
41
ns
t
PHL
2.0
4.5
6.0
195
39
33
245
49
42
295
59
50
t
PLH
Maximum Propagation Delay, Clock to Ripple Carry Out
(Figures 3 and 8)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
t
PHL
2.0
4.5
6.0
215
43
37
270
54
46
325
65
55
t
PHL
Maximum Propagation Delay, Reset to Ripple Carry Out
(HC160A Only)
(Figures 4 and 8)
2.0
4.5
6.0
220
44
37
275
55
47
330
66
56
ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 3 and 8)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
C
in
Maximum Input Capacitance − 10 10 10 pF
*Applies to noncascaded/nonsynchronously clocked configurations only. With synchronously cascaded counters, (1) Clock to Ripple Carry Out
propagation delays, (2) Enable T or Enable P to Clock setup times, and (3) Clock to Enable T or Enable P hold times determine f
max
. However,
if Ripple Carry Out of each stage is tied to the Clock of the next stage (nonsynchronously clocked), the f
max
in the table above is applicable.
See Applications Information in this data sheet.
C
PD
Power Dissipation Capacitance (Per Package)*
Typical @ 25°C, V
CC
= 5.0 V
pF
60
*Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC
2
f + I
CC
V
CC
.
MC74HC160A
http://onsemi.com
5
TIMING REQUIREMENTS (Input t
r
= t
f
= 6 ns)
Symbol Parameter
V
CC
V
Guaranteed Limit
Unit
− 55 to
25°C
v 85°C v 125°C
t
su
Minimum Setup Time, Preset Data Inputs to Clock
(Figure 6)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
t
su
Minimum Setup Time, Load to Clock
(Figure 6)
2.0
4.5
6.0
135
27
23
170
34
29
205
41
35
ns
t
su
Minimum Setup Time, Enable T or Enable P to Clock
(Figure 7)
2.0
4.5
6.0
200
40
34
250
50
43
300
60
51
ns
t
h
Minimum Hold Time, Clock to Preset Data Inputs
(Figure 6)
2.0
4.5
6.0
50
10
9
65
13
11
75
15
13
ns
t
h
Minimum Hold Time, Clock to Load
(Figure 6)
2.0
4.5
6.0
3
3
3
3
3
3
3
3
3
ns
t
h
Minimum Hold Time, Clock to Enable T or Enable P
(Figure 7)
2.0
4.5
6.0
3
3
3
3
3
3
3
3
3
ns
t
rec
Minimum Recovery Time, Reset Inactive to Clock
(Figure 4)
2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
ns
t
rec
Minimum Recovery Time, Load Inactive to Clock
(Figure 6)
2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
ns
t
w
Minimum Pulse Width, Clock
(Figure 3)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
t
w
Minimum Pulse Width, Reset
(Figure 4)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
t
r
, t
f
Maximum Input Rise and Fall Times
(Figure 3)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
MC74HC160A
http://onsemi.com
6
FUNCTION DESCRIPTION
The HC160A is a programmable 4−bit synchronous
counters that feature parallel Load, synchronous or
asynchronous Reset, a Carry Output for cascading, and
count−enable controls. The HC160A is a BCD counter with
asynchronous Reset.
INPUTS
Clock (Pin 2)
The internal flip−flops toggle and the output count
advances with the rising edge of the Clock input. In addition,
control functions, such as loading occur with the rising edge
of the Clock input.
Preset Data Inputs P0, P1, P2, P3 (Pins 3, 4, 5, 6)
These are the data inputs for programmable counting.
Data on these pins may be synchronously loaded into the
internal flip−flops and appear at the counter outputs. P0 (pin
3) is the least−significant bit and P3 (pin 6) is the
most−significant bit.
OUTPUTS
Q0, Q1, Q2, Q3 (Pins 14, 13, 12, 11)
These are the counter outputs (BCD or binary). Q0 (pin
14) is the least−significant bit and Q3 (pin 11) is the
most−significant bit.
Ripple Carry Out (Pin 15)
When the counter is in its maximum state (1001 for the
BCD counters or 1111 for the binary counters), this output
goes high, providing an external look−ahead carry pulse that
may be used to enable successive cascaded counters. Ripple
Carry Out remains high only during the maximum count
state. The logic equation for this output is:
Ripple Carry Out = Enable T Q0 Q1
Q2 Q3
for BCD counters
CONTROL FUNCTIONS
Resetting
A low level on the Reset pin (pin 1) resets the internal
flip−flops and sets the outputs (Q0 through Q3) to a low
level. The HC160A resets asynchronously.
Loading
With the rising edge of the Clock, a low level on Load (pin
9) loads the data from the Preset Data Input pins (P0, P1, P2,
P3) into the internal flip−flops and onto the output pins, Q0
through Q3. The count function is disabled as long as Load
is low.
Although the HC160A is a BCD counters, they may be
programmed to any state. If they are loaded with a state
disallowed in BCD code, they will return to their normal
count sequence within two clock pulses (see the Output State
Diagram).
Count Enable/Disable
These devices have two count−enable control pins:
Enable P (pin 7) and Enable T (pin 10). The devices count
when these two pins and the Load pin are high. The logic
equation is:
Count Enable = Enable P Enable T Load
The count is either enabled or disabled by the control
inputs according to Table 1. In general, Enable P is a
count−enable control; Enable T is both a count−enable and
a Ripple−Carry Output control.
Table 1. COUNT ENABLE/DISABLE
Control Inputs Result at Outputs
Load Enable P Enable T Q0 − Q3 Ripple Carry Out
H H H Count
High when
Q0−Q3 are max-
imum*
L H H No Count
X L H No Count High when
Q0−Q3 are max-
imum*
X X L No Count L
*Q0 through Q3 are maximum for the HC160A when Q3 Q2 Q1 Q0
= 1001.
01234
5
6
7
89101112
13
14
15
Figure 2. Output State Diagrams HC160A BCD Counters
P1-P3P4-P6P7-P9P10-P12

MC74HC160ADR2G

Mfr. #:
Buy MC74HC160ADR2G
Manufacturer:
ON Semiconductor
Description:
Counter Shift Registers IC COUNTER 4-BIT SYNC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet