It is possible to use an external reference oscillator in
place of a crystal to drive the VCO. AC-couple the exter-
nal oscillator to XTAL2 with a 1000pF capacitor. Drive
XTAL2 with a signal level of approximately 500mV
P-P
.
AC-couple XTAL1 to ground with a 1000pF capacitor.
Data Filter
The data filter is implemented as a 2nd-order lowpass
Sallen-Key filter. The pole locations are set by the com-
bination of two on-chip resistors and two external
capacitors. Adjusting the value of the external capaci-
tors changes the corner frequency to optimize for differ-
ent data rates. The corner frequency should be set to
approximately 1.5 times the fastest expected data rate
from the transmitter. Keeping the corner frequency near
the data rate rejects any noise at higher frequencies,
resulting in an increase in receiver sensitivity.
The configuration shown in Figure 1 can create a
Butterworth or Bessel response. The Butterworth filter
offers a very flat amplitude response in the passband
and a rolloff rate of 40dB/decade for the two-pole filter.
The Bessel filter has a linear phase response, which
works well for filtering digital data. To calculate the
value of C7 and C6, use the following equations, along
with the coefficients in Table 1:
where f
C
is the desired 3dB corner frequency.
For example, to choose a Butterworth filter response
with a corner frequency of 5kHz:
Choosing standard capacitor values changes C7 to
470pF and C6 to 220pF, as shown in the
Typical
Application Circuit
.
Data Slicer
The data slicer takes the analog output of the data filter
and converts it to a digital signal. This is achieved by
using a comparator and comparing the analog input to
a threshold voltage. One input is supplied by the data
filter output. Both comparator inputs are accessible off-
chip to allow for different methods of generating the
slicing threshold, which is applied to the second com-
parator input.
The suggested data slicer configuration uses a resistor
(R1) connected between DSN and DSP with a capaci-
tor (C8) from DSN to DGND (Figure 2). This configura-
tion averages the analog output of the filter and sets the
threshold to approximately 50% of that amplitude. With
this configuration, the threshold automatically adjusts
as the analog signal varies, minimizing the possibility
for errors in the digital data. The values of R1 and C8
affect how fast the threshold tracks to the analog ampli-
tude. Be sure to keep the corner frequency of the RC
circuit much lower than the lowest expected data rate.
Note that a long string of zeros or ones can cause the
threshold to drift. This configuration works best if a cod-
ing scheme, such as Manchester coding, which has an
equal number of zeros and ones, is used.
To prevent continuous toggling of DATAOUT in the
absence of an RF signal due to noise, add hysteresis to
the data slicer as shown in Figure 3.
C
kkHz
pF
C
7
1 000
1 414 100 3 14 5
450
.
..
=
()( )()()
Ω
66
1 414
4 100 3 14 5
225
.
.
=
()( )( )( )
kkHz
pF
Ω
C
b
ak f
C
a
kf
C
C
7
100
6
4 100
=
()()
()
=
()()
()
π
π
MAX7034
315MHz/434MHz ASK Superheterodyne
Receiver
10
RSSI
R
DF1
100kΩ
R
DF2
100kΩ
C7
19
DFO
21
OPP
22
DFFB
C6
MAX7034
FILTER TYPE a b
Butterworth (Q = 0.707) 1.414 1.000
Bessel (Q = 0.577) 1.3617 0.618
Figure 1. Sallen-Key Lowpass Data Filter
Table 1. Coefficents to Calculate C7 and C6
Peak Detector
The peak-detector output (PDOUT), in conjunction with
an external RC filter, creates a DC output voltage equal
to the peak value of the data signal. The resistor pro-
vides a path for the capacitor to discharge, allowing the
peak detector to dynamically follow peak changes of
the data-filter output voltage. For faster data slicer
response, use the circuit shown in Figure 4. For more
details on hysteresis and peak-detector applications,
refer to Maxim Application Note 3671,
Data Slicing
Techniques for UHF ASK Receivers
.
Layout Considerations
A properly designed PCB is an essential part of any
RF/microwave circuit. On high-frequency inputs and
outputs, use controlled-impedance lines and keep them
as short as possible to minimize losses and radiation.
At high frequencies, trace lengths that are on the order
of λ/10 or longer act as antennas.
Keeping the traces short also reduces parasitic induc-
tance. Generally, 1 inch of a PCB trace adds about
20nH of parasitic inductance. The parasitic inductance
can have a dramatic effect on the effective inductance
of a passive component. For example, a 0.5 inch trace
connecting a 100nH inductor adds an extra 10nH of
inductance or 10%.
To reduce the parasitic inductance, use wider traces
and a solid ground or power plane below the signal
traces. Also, use low-inductance connections to ground
on all GND pins, and place decoupling capacitors
close to all power-supply pins.
Control Interface Considerations
When operating the MAX7034 with a +4.5V to +5.5V
supply voltage, the SHDN pin can be driven by a
microcontroller with either +3.0V or +5V interface logic
levels. When operating the MAX7034 with a +3.0V to
+3.6V supply, only +3.0V logic from the microcontroller
is allowed.
MAX7034
315MHz/434MHz ASK Superheterodyne
Receiver
11
DATA
SLICER
R1
25
DATAOUT
20
DSN
19
DFO
23
DSP
C8
MAX7034
DATA
SLICER
R3
R2
R*
R1
25
DATAOUT
*OPTIONAL
23
DSP
19
DFO
20
DSN
C8
MAX7034
Figure 3. Generating Data Slicer Hysteresis
DATA
SLICER
25kΩ
25
DATAOUT
20
DSN
19
DFO
26
PDOUT
23
DSP
MAX7034
47nF
Figure 4. Using PDOUT for Faster Startup
Figure 2. Generating Data Slicer Threshold
MAX7034
315MHz/434MHz ASK Superheterodyne
Receiver
12
Typical Application Circuit
XTAL1
R2
R3
TO/FROM µP
POWER-DOWN
DATA OUT
AVDD
LNAIN
LNASRC
AGND
AVDD
MIXIN1
MIXIN2
AGND
IRSEL
MIXOUT
DGND
DVDD
Y1
IF FILTER
COMPONENT VALUES
IN TABLE 2
***SEE THE
MIXER
SECTION.
*SEE THE
PHASE-LOCKED
LOOP
SECTION.
**SEE THE
VOLTAGE
REGULATOR
SECTION.
GND
IN OUT
*
**
***
C5
C10
C9
C4
C3
C2
C1
C11
C12
C15
C7
R1
C13
RF INPUT
L3
L2
L1
V
DD3
V
DD3
IF V
DD
IS
3.0V TO 3.6V
4.5V TO 5.5V
CREATED BY LDO,
AVAILABLE AT AVDD
(PIN 2)
CONNECTED TO V
DD
CONNECTED TO V
DD
GROUNDED
THEN V
DD3
IS AND EN_REG IS
X1
(SEE TABLE)
V
DD
V
DD
C14
C6 C8
EN_REG
XTALSEL
IFIN1
IFIN2
DFO
DSN
OPP
DFFB
DSP
DATAOUT
PDOUT
SHDN
XTAL2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
V
DD5
LNAOUT
MAX7034

MAX7034AUI+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
RF Receiver 315MHz/433MHz ASK Superheterodyne Rec
Lifecycle:
New from this manufacturer.
Delivery:
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