MAX7034
315MHz/434MHz ASK Superheterodyne
Receiver
Pin Description (continued)
PIN NAME FUNCTION
4 LNASRC
Low-Noise Amplifier Source for external Inductive Degeneration. Connect inductor to ground to set
LNA input impedance. See the Low-Noise Amplifier section.
5, 10 AGND Analog Ground
6 LNAOUT
Low-Noise Amplifier Output. Connect to mixer input through an LC tank filter. See the Low-Noise
Amplifier section.
8 MIXIN1
1st Differential Mixer Input. Connect to LC tank filter from LNAOUT through a 100pF capacitor. See
the Typical Application Circuit.
9 MIXIN2
2nd Differential Mixer Input. Connect to V
DD3
side of the LC tank filter through a 100pF capacitor. See
the Typical Application Circuit.
11 IRSEL
Image-Rejection Select. Set V
IRSEL
= 0V to center image rejection at 315MHz. Leave IRSEL
unconnected to center image rejection at 375MHz. Set V
IRSEL
= DVDD to center image rejection at
434MHz. See the Mixer section.
12 MIXOUT 330Ω Mixer Output. Connect to the input of the 10.7MHz bandpass filter.
13 DGND Digital Ground
14 DVDD
Positive Digital Supply Voltage. Connect to both of the AVDD pins. Bypass to DGND with a 0.01μF
capacitor as close as possible to the pin (see the Typical Application Circuit).
15 EN_REG
Regulator Enable. Connect to V
DD5
to enable internal regulator. Pull this pin low to allow device
operation between +3.0V and +3.6V. See the Voltage Regulator section.
16 XTALSEL
Crystal Divider Ratio Select. Drive XTALSEL low to select f
LO
/f
XTAL
ratio of 64, or drive XTALSEL high
to select f
LO
/f
XTAL
ratio of 32.
17 IFIN1
1st Differential Intermediate-Frequency Limiter Amplifier Input. Connect to the output of a 10.7MHz
bandpass filter.
18 IFIN2
2nd Differential Intermediate-Frequency Limiter Amplifier Input. Bypass to AGND with a 1500pF
capacitor as close as possible to the pin.
19 DFO Data Filter Output
20 DSN Negative Data Slicer Input
21 OPP Noninverting Op-Amp Input for the Sallen-Key Data Filter
22 DFFB Data Filter Feedback Node. Input for the feedback of the Sallen-Key data filter.
23 DSP Positive Data Slicer Input
24 V
DD5
+5V Supply Voltage. Bypass to AGND with a 0.01μF capacitor as close as possible to the pin. For
+5V operation, V
DD5
is the input to an on-chip voltage regulator whose +3.4V output appears at
AVDD pin 2. (see the Voltage Regulator section and the Typical Application Circuit).
25 DATAOUT Digital Baseband Data Output
26 PDOUT Peak-Detector Output
27 SHDN
Power-Down Select Input. Drive high to power up the IC. Internally pulled down to AGND with a
100kΩ resistor.
28 XTAL2 C r ystal Inp ut 2. C an al so b e d r i ven w i th an exter nal r efer ence osci l l ator . S ee the C r ystal O sci l l ator secti on.
7
MAX7034
315MHz/434MHz ASK Superheterodyne
Receiver
8
Functional Diagram
LNAOUT MIXIN1 MIXIN2
90˚
IFIN1MIXOUT IFIN2
RSSI
R
DF2
100kΩ
R
DF1
100kΩ
DIVIDE
BY 64
VCO
LOOP
FILTER
PHASE
DETECTOR
CRYSTAL
DRIVER
POWER-
DOWN
IF LIMITING
AMPS
7
LNASRC
DATA
SLICER
DATA
FILTER
Q
I
IMAGE
REJECTION
3.4V REG
24
2
IRSEL
13
5, 10
AVDD
V
DD5
AVDD
DVDD
DGND
AGND
LNAIN
3
XTALSEL
16
XTAL1
1
XTAL2
28
SHDN
27
DATAOUT
25
DSN
20
DSP
23
DFO
19
PDOUT
26
OPP
21
DFFB
22
4 15 6 8 9 11 12 17 18
EN_REG
÷2
÷1
MAX7034
LNA
14
Detailed Description
The MAX7034 CMOS superheterodyne receiver and a
few external components provide the complete receive
chain from the antenna to the digital output data.
Depending on signal power and component selection,
data rates can be as high as 33kbps Manchester
(66kbps NRZ).
The MAX7034 is designed to receive binary ASK data
modulated in the 300MHz to 450MHz frequency range.
ASK modulation uses a difference in amplitude of the
carrier to represent logic 0 and logic 1 data.
Voltage Regulator
For operation with a single +4.5V to +5.5V supply voltage,
connect V
DD5
and the EN_REG pin to the supply voltage.
An on-chip voltage regulator drives one of the AVDD pins
(pin 2) to approximately +3.4V. For proper operation,
DVDD and both AVDD pins must be connected together.
For operation with a single +3.0V to +3.6V supply voltage,
connect both the AVDD pins, DVDD, and V
DD5
to the
supply voltage and connect the EN_REG pin to ground
(which disables the internal voltage regulator). If the
MAX7034 is powered from +3.0V to +3.6V, the perfor-
mance is limited to the -40°C to +105°C range.
In either supply voltage mode, bypass V
DD5
, DVDD, and
the pin 7 AVDD pin to AGND with 0.01μF capacitors, and
the pin 2 AVDD to AGND with a 0.1μF capacitor, all
placed as close as possible to the pins.
Low-Noise Amplifier
The LNA is an nMOS cascode amplifier with off-chip
inductive degeneration. The gain and noise figures are
dependent on both the antenna matching network at
the LNA input and the LC tank network between the
LNA output and the mixer inputs.
The off-chip inductive degeneration is achieved by
connecting an inductor from LNASRC to AGND. This
inductor sets the real part of the input impedance at
LNAIN, allowing for a more flexible input impedance
match, such as a typical printed-circuit board (PCB)
trace antenna. A nominal value for this inductor with a
50Ω input impedance is 15nH, but is affected by the
PCB trace.
The LC tank filter connected to LNAOUT comprises L1
and C9 (see the
Typical Application Circuit
). Select L1
and C9 to resonate at the desired RF input frequency.
The resonant frequency is given by:
where:
L
TOTAL
= L1 + L
PARASITICS
.
C
TOTAL
= C9 + C
PARASITICS
.
f
LC
RF
TOTAL TOTAL
=
×
1
2π
MAX7034
315MHz/434MHz ASK Superheterodyne
Receiver
9
L
PARASITICS
and C
PARASITICS
include inductance and
capacitance of the PCB traces, package pins, mixer
input impedance, etc. These parasitics at high frequen-
cies cannot be ignored, and can have a dramatic effect
on the tank filter center frequency. The total parasitic
capacitance is generally between 4pF and 6pF.
Mixer
A unique feature of the MAX7034 is the integrated
image rejection of the mixer. This device eliminates the
need for a costly front-end SAW filter for most applica-
tions. Advantages of not using a SAW filter are
increased sensitivity, simplified antenna matching, less
board space, and lower cost.
The mixer cell is a pair of double balanced mixers that
perform an IQ downconversion of the RF input to the
10.7MHz IF from a low-side injected LO (i.e., f
LO
= f
RF
-
f
IF
). The image-rejection circuit then combines these
signals to achieve 44dB of image rejection. Low-side
injection is required due to the on-chip image-rejection
architecture. The IF output is driven by a source follow-
er biased to create a driving-point impedance of 330Ω;
this provides a good match to the off-chip 330Ω ceram-
ic IF filter.
The IRSEL pin is a logic input that selects one of the
three possible image-rejection frequencies. When V
IRSEL
= 0V, the image rejection is tuned to 315MHz. V
IRSEL
=
V
DVDD
/2 tunes the image rejection to 375MHz, and
V
IRSEL
= V
DVDD
tunes the image rejection to 434MHz.
The IRSEL pin is internally set to V
DVDD
/2 (image rejec-
tion at 375MHz) when it is left unconnected, thereby
eliminating the need for an external V
DVDD
/2 voltage.
Phase-Locked Loop
The PLL block contains a phase detector, charge
pump, integrated loop filter, VCO, asynchronous 64x
clock divider, and crystal oscillator driver. Besides the
crystal, this PLL does not require any external compo-
nents. The VCO generates a low-side LO. The relation-
ship between the RF, IF, and crystal frequencies is
given by:
where:
M = 1 (V
XTALSEL
= V
DVDD
) or 2 (V
XTALSEL
= 0V)
To allow the smallest possible IF bandwidth (for best sen-
sitivity), minimize the tolerance of the reference crystal.
Intermediate Frequency and RSSI
The IF section presents a differential 330Ω load to pro-
vide matching for the off-chip ceramic filter. The six
internal AC-coupled limiting amplifiers produce an
overall gain of approximately 65dB, with a bandpass-
filter-type response centered near the 10.7MHz IF fre-
quency with a 3dB bandwidth of approximately 10MHz.
The RSSI circuit demodulates the IF by producing a DC
output proportional to the log of the IF signal level, with
a slope of approximately 14.2mV/dB.
Applications Information
Crystal Oscillator
The crystal oscillator in the MAX7034 is designed to
present a capacitance of approximately 3pF between
the XTAL1 and XTAL2. If a crystal designed to oscillate
with a different load capacitance is used, the crystal is
pulled away from its intended operating frequency,
introducing an error in the reference frequency.
Crystals designed to operate with higher differential
load capacitance always pull the reference frequency
higher. For example, a 4.7547MHz crystal designed to
operate with a 10pF load capacitance oscillates at
4.7563MHz with the MAX7034, causing the receiver to
be tuned to 315.1MHz rather than 315.0MHz, an error
of about 100kHz, or 320ppm. It is very important to
use a crystal with a load capacitance that is equal to
the capacitance of the MAX7034 crystal oscillator
plus PCB parasitics.
In actuality, the oscillator pulls every crystal. The crys-
tal’s natural frequency is really below its specified fre-
quency, but when loaded with the specified load
capacitance, the crystal is pulled and oscillates at its
specified frequency. This pulling is already accounted
for in the specification of the load capacitance.
Additional pulling can be calculated if the electrical
parameters of the crystal are known. The frequency
pulling is given by:
where:
f
P
is the amount the crystal frequency pulled in ppm.
C
M
is the motional capacitance of the crystal.
C
CASE
is the case capacitance.
C
SPEC
is the specified load capacitance.
C
LOAD
is the actual load capacitance.
When the crystal is loaded as specified (i.e., C
LOAD
=
C
SPEC
), the frequency pulling equals zero.
f
C
CCCC
P
M
CASE LOAD CASE SPEC
=
++
×
2
11
10
6
-
f
ff
M
XTAL
RF IF
=
×
-
32

MAX7034AUI+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
RF Receiver 315MHz/433MHz ASK Superheterodyne Rec
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union