MEMSIC MXP7205VW Rev.C Page 11 of 12 8/2/2011
Name Bit Position Definition
OP1:OP0 14:13 Opcode - Identifies contents of Read or Write data in D9:D0 - copied from MOSI if request granted
P 12 Parity - Ensures odd parity for bits 15:0 of MISO
ST1:ST0 11:10 Status - Always ‘11’ for non-sensor response
ES1:ES0 9:8 Exception Status - Always ’10’ for non-sensor response
D7:D0 7:0 Read Data/Error Data/Status
SE 2 SPI Error - Set if there is an incorrect number of SCK clock pulses during a data transfer frame
RE 1 Request Error - Set to ‘1’ for illegal, or unknown requests
DU 0 Data Unavailable - Not used
Slave Response MISO Bit Definition
Summary of MXP7205VW SPI protocol:
If bit 13 (SEN) of the request is a ‘1’, then the data transfer is a read of one of the accelerometer output registers. Bits 15 (SQ1),
14 (SQ0), and 12 (SQ2) are the sequence bits. This field provides the system with a means of synchronizing the data samples
received from the sensors. Bits 3:0 are the logical channel bits, LC3:LC0. These bits determine whether the x or y axis data is
being read, and whether the MSB or LSB byte is being read. None of the other bits in the request have any meaning.
If bit 13 (SEN) of the request is a ‘0’, then the data transfer is a write or read of the MXP7205VW control register. Bits 15
(OP1), and 14 (OP0) define whether the request is a write (OP1:OP0 = 01), or a read (OP1:OP0 = 10). Since the MXP7205VW
has only one control register, the address bits in the request are irrelevant. All requests with SEN=0, are assumed to be directed
to the 8-bit control register. The only other bits that have meaning, besides 15:13, for a slave data request, are the data bits 7:0,
for the case of a write to the control register.
The errors that are detected for a sensor data request are: 1. CNC = 1, chip is in power down state; and 2. HE = 1, heater control
loop is out of regulation.
If the number of SCK rising edges during a data transfer (period of time from the falling edge of SSB to the rising edge of SSB)
is different from 16, then bit 2 (SE) will be set. If the request does not correspond to any of the requests defined in this
specification, then bit 1 (RE) will be set. The remaining bits in the response, for these errors, will correspond to those given in
the table of Slave Data Response.
The response on MISO during the first command following a reset will be a slave data error response with RE = 1, DU = 1.
MXP7205VW CONTROL REGISTER
The MXP7205VW contains a single 8-bit control register. This register can be written to and read by the master device. The bit
definitions are shown in following table, followed by a description of each control bit.
MSB LSB
7 6 5 4 3 2 1 0
DAT1 DAT0 RFILT FTST1 FTST0 TC ST PD
MXP7205VW Control Register
DAT1:DAT0 - These 2 bits determine how the accelerometer output registers will be updated.
RFILT - Writing this bit to a ‘1’ resets the digital filters for the x and y/z channels. The bit must be cleared for normal operation
to resume. Can be used in the testing of the filters. While the digital filters are in reset (RFILT=1), the x and y acceleration
outputs will be 0.
FTST1:FTST0 - These bits are used to facilitate testing of the digital filter. The different modes of operation are described in
following table. Both the x channel and y/z channel filters are affected in the same way.
FTST1 FTST0 Definition
0 0 Normal operating mode
