MEMSIC MXP7205VW Rev.C Page 8 of 12 8/2/2011
SERIAL PERIPHERAL INTERFACE PROTOCOL
The Serial Peripheral Interface (SPI) is a synchronous serial communication subsystem. The SPI described here is a 16-bit
variation of the original 8-bit design. There are four pins associated with the SPI: 1. SCK (serial clock), 2. MISO (master in/
slave out), 3. MOSI (master out/ slave in), and 4. SSB (slave select bar). Internal to each device on the SPI bus is a 16-bit shift
register. Devices can operate in either a master or slave role. There can only be one master on the SPI bus at any given time. The
pins MISO, MOSI, and SCK are tied together for all devices on the bus. To initiate a data transfer, the master device pulls SSB
low on the slave device that it wishes to communicate with. Internal to the slave device this accomplishes two things: 1. It allows
SCK (generated by the master) to pass through to the shift register, and 2. It enables output MISO (all unselected slave devices
on the bus will have MISO tri-stated). During an SPI transfer, a 16-bit word is shifted out of MISO, while a different 16-bit word
is simultaneously shifted into MOSI, synchronous with clock SCK (for the master device, the roles of MISO and MOSI are
reversed). Another way to view the transfer is that a 16-bit shift register in the master, and another 16-bit shift register in the
slave are connected as a circular 32-bit shift register. When a transfer occurs, this distributed shift register is shifted 16 bit
positions; thus the data words in the master and slave are effectively exchanged.
The SPI on the MXP7205VW is designed to operate only in the slave mode. It uses the protocol CPHA = 0, CPOL = 0, that is,
data changes on MOSI and MISO on the falling edge of SCK, and is clocked into the shift register on the rising edge of SCK.
When the MXP7205VW is selected as the slave device, 16-bits of data, MSB first, are simultaneously shifted from the master to
the slave, and from the slave to the master on the 16 rising edges of SCK. After the 16th rising edge of SCK, the slave shift
register will contain the 16-bit word that was transferred from the master. Internal to the MXP7205VW there is a 16-bit bus that
serves both as the address bus and the data bus. Immediately after the 16th rising edge of SCK, the internal bus will be driven by
the shift register outputs, and will be used as the address bus. When SCK falls, the address on the internal bus will be latched into
the address decoders. During the time between the last falling edge of SCK and the next falling edge of SSB, data will be placed
on the internal bus in accordance with the instruction received by the address decoders. On the rising edge of SSB, the data on
the internal bus will be latched into the appropriate register. The rising edge of SSB also signals the end of the data transfer.
There are 2 types of data transfers supported by the MXP7205VW SPI: 1.Master reading the x and y/z channel MSB and LSB
accelerometer output registers, and 2. Master reading and writing the MXP7205VW 8-bit control register. If bit 13, “SEN”, of
the word written from the master to the MXP7205VW is hi, then the instruction is a read of an accelerometer output register. If
bit 13 is low, then the instruction is either a read or write of the MXP7205VW control register.
The protocol for reading the accelerometer output registers is shown in following tables
Sensor Data Request (MOSI):
MSB
LSB
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ1 SQ0 SEN SQ2 - - - - - - - - LC3 LC2 LC1 LC0
- - 1 - Accelerometer output LSB register, x-channel - - 0 0
- - 1 - Accelerometer output LSB register, y/z-channel - - 0 1
- - 1 - Accelerometer output MSB register, x-channel - - 1 0
- - 1 - Accelerometer output MSB register, y/z-channel - - 1 1
Sensor Data Request
Name Bit Position Definition
SQ2:SQ0 15,14,12 Sequence identifier - used for synchronizing samples
SEN 13 SEN = 1, sensor data read; SEN = 0, control register read or write.
LC3:LC0 3:0 Logical channel select
11:4 Not used for sensor data request.
Sensor Data Request MOSI Bit Definition
