ISL1536IRZ-T13

7
FN6508.4
February 15, 2013
Applications Information
Product Description
The ISL1536 consists of two sets of high-power line driver
amplifiers that can be connected for full duplex differential
line transmission. The amplifiers are designed to be used
with ADSL2+ signals up to 2.2MHz. Each amplifier has
identical positive gain connections resulting in optimum
common-mode rejection. A typical interface circuit
configuration is shown in Figure 15.
Integrated Components
ISL1536 integrates bias and feedback resistors, minimizing
the number of external components. The gain is fixed at
+12.85V/V.
The VBAB and VBCD pins also integrate a pair of 7.5kΩ and
50kΩ resistors on each port to bias the line driver for single
and dual supply usage. When powering the line driver with a
single supply, VBAB and VBCD pins are floated. When using
dual supplies, VBAB and VBCD pins are grounded.
Integration of these components in the line driver minimizes
assembly cost and board space.
Impedance Matching
R
B
in Figure 15 depends on the line impedance and
transformer’s turns ratio. Line impedance is characterized to
be 100Ω across tip and ring. If a 1:N tranformer is used, R
B
can be calculated according to Equation 1:
-
+
-
+
-
+
-
+
RECEIVER
OUTPUT -
RECEIVER
OUTPUT +
DRIVER
INPUT
R
G*
R
F*
R
F*
R
F
R
R
IN
R
R
IN
R
F
R
B
R
B
TIP
RING
RECEIVE
AMPLIFIERS
Z
LINE
*Values are internally
set for line driver
DRIVER
INPUT
FIGURE 15. TYPICAL INTERFACE CIRCUIT CONFIGURATION
RB
100
N
2
----------
0.5×=
⎝⎠
⎛⎞
(EQ. 1)
8
FN6508.4
February 15, 2013
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at
any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements
of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
For additional products, see www.intersil.com/en/products.html
Revision History
DATE REVISION CHANGE
November 20, 2012 FN6508.4 Added Note 3 to “Ordering Information” on page 1.
Changed HBM from 3kV to 4kV in “Absolute Maximum Ratings” on page 3.
Changed MM from 300V to 250V in “Absolute Maximum Ratings” on page 3
Added Note 5 to “Electrical Specifications” table on page 4.
March 8, 2010 FN6508.3 On page 4, changed the “Maximum Operating Supply Voltage” TYP from ±12.6V to ±13.2V
February 8, 2010 On page 3 in the “Electrical Specifications” table, changed V
OUT
-DIS Max spec from ±300mV to ±800mV
May 29, 2009 Added Revision History beginning from rev 3.
Changed the logic high level (VIH) on page 3 from Min 2.0V to Min 2.2V, which is consistent with the intended
applications (AFE output logic high levels are typically at 3.3V with 2.4V minimum) while providing added margin
to internal threshold variation.
On page 1 in the first paragraph, changed: "This device features a high drive capability of 400mA while
consuming only 3mA..." to "This device features a high drive capability of 400mA while consuming only 4mA...".
Added Theta JA and applicable note to “Thermal Information” on page 3.
Removed VS, Supply Voltage row in spec table. Added Maximum and Minimum Operating Supply Voltages
(V
S(MAX)
and V
S(MIN)
) with typical specs of ±12.6V and ±7.5V to “SUPPLY CHARACTERISTICS” on page 4.
Added “DISAB = DISCD = 0” to “Electrical Specifications” table common conditions.
9
FN6508.4
February 15, 2013
ISL1536
Package Outline Drawing
L16.4x4E
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 4/08
located within the zone indicated. The pin #1 identifier may be
Unless otherwise specified, tolerance : Decimal ± 0.05
Tiebar shown (if present) is a non-functional feature.
The configuration of the pin #1 identifier is optional, but must be
between 0.15mm and 0.30mm from the terminal tip.
Dimension b applies to the metallized terminal and is measured
Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
6.
either a mold or mark feature.
3.
5.
4.
2.
Dimensions are in millimeters.1.
NOTES:
BOTTOM VIEW
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
BOTTOM VIEW
SIDE VIEW
2 . 50 ± 0 . 05
SEE DETAIL "X"
0.30 ± 0 . 05
BASE PLANE
PIN #1 INDEX AREA
5
8
( 3 . 8 TYP )
( 2 . 50 TYP )
( 12X 0 . 65 )
( 16X 0 .30 )
( 16 X 0 . 6 )
0 . 9 ± 0 . 1
16X 0 . 4 ± 0 . 05
0 . 2 REF
0 . 00 MIN.
0 . 05 MAX.
C
5
4
0.10 CM
INDEX AREA
(4X) 0.15
PIN 1
6
4.00
12
4.00
9
A
B
4
0.65
12X
13
4X 1.95
16
1
6
0.08 C
C
SEATING PLANE
0.10
C
AB

ISL1536IRZ-T13

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Buffers & Line Drivers Dual Ch ADSL2+ Line- Dvr(Low Pwr Dif Amp)
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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