13
Notes:
11a. Systematic Jitter contributed by the transmitter is dened as the combination of Duty Cycle Distortion and Data Dependent Jitter. Systematic
Jitter is measured at 50% threshold using a 155.52 MBd (77.5 MHz square-wave), 2
23
- 1 psuedorandom data pattern input signal.
11b. Duty Cycle Distortion contributed by the transmitter is measured at the 50% threshold of the optical output signal using an IDLE Line State,
125 MBd (62.5 MHz square-wave), input signal.
11c. Data Dependent Jitter contributed by the transmitter is specied with the FDDI test pattern described in FDDI PMD Annex A.5.
12a. Random Jitter contributed by the transmitter is specied with a 155.52 MBd (77.5 MHz square-wave) input signal.
12b. Random Jitter contributed by the transmitter is specied with an IDLE Line State, 125 MBd (62.5 MHz square-wave) input signal. See Applica-
tion Information - Transceiver Jitter Performance Section of this data sheet for further details.
Receiver Optical and Electrical Characteristics
HFBR-57E0LZ /PZ(T
C
= 0 ºC to +70 ºC, V
CC
= 2.97 V to 3.63 V)
HFBR-57E0ALZ/APZ (T
C
= -40 ºC to +85 ºC, V
CC
= 2.97 V to 3.63 V)
Parameter Symbol Minimum Typical Maximum Units Notes
Input Optical Power minimum at Window Edge
OC-3
FE
P
IN MIN
(W)
-30
-31
dBm avg
13a,
Figure 4
13b
Input Optical Power at Eye Center
OC-3
FE
P
IN MIN
(C)
-31
-31.8
dBm avg 14a,
Figure 4
14b
Input Optical Power Maximum
OC-3
FE
P
IN MAX
-14
-14
dBm avg
13a
13b
Operating Wavelength
O
1270 1380 nm
Systematic Jitter Contributed by the Receiver
OC-3
SJ 0.11 1.2 ns p-p 15a
Duty Cycle Distortion Contributed by the Receiver
FE
DCD 0.08 0.4 ns p-p 15b
Data Dependent Jitter Contributed by the Receiver
FE
DDJ 0.02 1.0 ns p-p 15c
Random Jitter Contributed by the Receiver
OC-3
FE
RJ
0.14
0.14
1.91
2.14
ns p-p
16a
16b
Loss of Signal - Deasserted
OC-3
FE
P
A
P
D
+
1.5 dB
-31
-33
dBm avg 17
Loss of Signal - Asserted P
D
-45 dBm avg 18
Loss of Signal - Hysteresis P
A
- P
D
1.5 dB
Loss of Signal Deassert Time (on to o) 0 2 100 μs 19
Loss of Signal Assert Time (o to on) 0 5 350 μs 20
Notes:
13a. This specication is intended to indicate the performance of the receiver section of the transceiver when Input Optical Power signal character-
istics are present per the following denitions. The Input Optical Power dynamic range from the minimum level (with a window time-width) to
the maximum level is the range over which the receiver is guaranteed to provide output data with a Bit Error Rate (BER) better than or equal
to 1 x 10
-10.
- At the Beginning of Life (BOL)
- Over the specied operating temperature and voltage ranges
- Input is a 155.52 MBd, 2
23
-1 PRBS data pattern with 72 “1” s and 72 “0”s inserted per the CCITT (now ITU-T) recommendation G.958 Appendix
I.
- Receiver data window time-width is 1.23 ns or greater for the clock recovery circuit to operate in. The actual test data window time-width
is set to simulate the eect of worst case optical input jitter based on the transmitter jitter values from the specication tables. The test
window time-width is 3.32 ns.
- Transmitter operating with a 155.52 MBd, 77.5 MHz square-wave, input signal to simulate any cross-talk present between the transmitter
and receiver sections of the transceiver.
14
13b. This specication is intended to indicate the performance of the receiver section of the transceiver when Input Optical Power signal characteristics are
present per the following denitions. The Input Optical Power dynamic range from the minimum level (with a window time-width) to the maximum
level is the range over which the receiver is guaranteed to provide output data with a Bit Error Rate (BER) better than or equal to 2.5 x 10
-10
.
At the Beginning of Life (BOL)
Over the specied operating temperature and voltage ranges
Input symbol pattern is the FDDI test pattern dened in FDDI PMD Annex A.5 with 4B/5B NRZI encoded data that contains a duty cycle base-line
wander eect of 50 kHz. This sequence causes a near worst case condition for inter-symbol interference.
Receiver data window time-width is 2.13 ns or greater and centered at mid-symbol. This worst case window time-width is the minimum allowed
eye-opening presented to the FDDI PHY PM_Data indication input (PHY input) per the example in FDDI PMD Annex E. This minimum window
time-width of 2.13 ns is based upon the worst case FDDI PMD Active Input Interface optical conditions for peak-to-peak DCD (1.0 ns), DDJ (1.2 ns)
and RJ (0.76 ns) presented to the receiver.
To test a receiver with the worst case FDDI PMD Active Input jitter condition requires exacting control over DCD, DDJ and RJ jitter compo nents that
is dicult to implement with production test equipment. The receiver can be equivalently tested to the worst case FDDI PMD input jitter condi-
tions and meet the minimum output data window time-width of 2.13 ns. This is accom plished by using a nearly ideal input optical signal (no DCD,
insignicant DDJ and RJ) and measuring for a wider window time-width of 4.6 ns. This is possible due to the cumula tive eect of jitter components
through their superposition (DCD and DDJ are directly additive and RJ components are rms additive). Specically, when a nearly ideal input optical
test signal is used and the maximum receiver peak-to-peak jitter contributions of DCD (0.4 ns), DDJ (1.0 ns), and RJ (2.14 ns) exist, the minimum
window time-width becomes 8.0 ns -0.4 ns - 1.0 ns - 2.14 ns = 4.46 ns, or conservatively 4.6 ns. This wider window time-width of 4.6 ns guarantees
the FDDI PMD Annex E minimum window time-width of 2.13 ns under worst case input jitter conditions to the Avago receiver.
Transmitter operating with an IDLE Line State pattern, 125 MBd (62.5 MHz square-wave), input signal to simulate any cross-talk present between
the trans mit ter and receiver sections of the transceiver.
14a. All conditions of Note 13a apply except that the measurement is made at the center of the symbol with no window time- width.
14b. All conditions of Note 13b apply except that the measurement is made at the center of the symbol with no window time-width.
15a. Systematic Jitter contributed by the receiver is dened as the combination of Duty Cycle Distortion and Data Dependent Jitter. Systematic Jitter is
measured at 50% threshold using a 155.52 MBd (77.5 MHz square- wave), 2
23
-1 psuedorandom data pattern input signal.
15b Duty Cycle Distortion contributed by the receiver is measured at the 50% threshold of the electrical output signal using an IDLE Line State,
125 MBd (62.5 MHz square-wave), input signal. The input optical power level is -20 dBm average.
15c. Data Dependent Jitter contributed by the receiver is specied with the FDDI DDJ test pattern described in the FDDI PMD Annex A.5. The input
optical power level is -20 dBm average.
16a. Random Jitter contributed by the receiver is specied with a 155.52 MBd (77.5 MHz square- wave) input signal.
16b. Random Jitter contributed by the receiver is specied with an IDLE Line State, 125 MBd (62.5 MHz square-wave), input signal. The input optical
power level is at maximum “P
IN MIN
(W)”. See Application Information - Transceiver Jitter Section for further information.
17. This value is measured during the transition from low to high levels of input optical power.
18. This value is measured during the transition from high to low levels of input optical power. At Loss of Signal assert, the receiver outputs Data
Out and Data Out Bar go to steady PECL levels High and Low respectively.
19. The Loss of Signal output shall be de-asserted within 100 μs after a step increase of the Input Optical Power.
20. Loss of Signal output shall be asserted within 350 μs after a step decrease in the Input Optical Power. At Loss of Signal Assert, the receiver
outputs Data Out and Data Out Bar go to steady PECL levels High and Low respectively.
21. The HFBR-57E0 transceiver complies with the requirements for the trade-os between center wavelength, spectral width, and rise/fall times
shown in Figure 3. This gure is derived from the FDDI PMD standard (ISO/IEC 9314-3 : 1990 and ANSI X3.166 - 1990) per the description in
ANSI T1E1.2 Revision 3. The interpretation of this gure is that values of Center Wavelength and Spectral Width must lie along the appropriate
Optical Rise/Fall Time curve.
Ordering Information
1300 nm LED (Operating Case Temperature 0 to +70 °C)
HFBR-57E0LZ Standard de-latch
HFBR-57E0PZ Bail de-latch
1300 nm LED (Operating Case Temperature -40 °C to +85 °C)
HFBR-57E0ALZ Standard de-latch
HFBR-57E0APZ Bail de-latch
EEPROM contents and/or label options
HFBR-57E0LZ-YYY Standard de-latch, 0 to +70°C
HFBR-57E0PZ-YYY Bail de-latch, 0 to +70°C
HFBR-57E0ALZ-YYY Standard de-latch, -40°C to +85°C
HFBR-57E0APZ-YYY Bail de-latch, -40°C to +85°C
Where YYY” is customer specic.
Handling Precaution
The HFBR-57E0xxZ is a pluggable module and is NOT designed for aqueous wash, IR reow or wave soldering pro-
cesses.
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2011 Avago Technologies. All rights reserved. Obsoletes AV01-0456EN
AV02-2810EN - Januaray 20, 2011

HFBR-57E0LZ

Mfr. #:
Manufacturer:
Broadcom / Avago
Description:
Fiber Optic Transmitters, Receivers, Transceivers MM LC SFP OC3/FE/TX- DIS STDDL RoHS
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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