7
Table 3. EEPROM Serial ID Memory Contents
Add Hex ASCII Add Hex ASCII Add Hex ASCII Add Hex ASCII
0 03 33 20 63 Note 3 95 Note 3
1 04 34 20 64 00 96 Note 5
2 07 35 20 65 12 97 Note 5
3 00 36 00 66 00 98 Note 5
4 00 37 00 67 00 99 Note 5
5 01, Note 6 38 17 68 Note 1 100 Note 5
6 20, Note 6 39 6A 69 Note 1 101 Note 5
7 00 40 48 H 70 Note 1 102 Note 5
8 00 41 46 F 71 Note 1 103 Note 5
9 00 42 42 B 72 Note 1 104 Note 5
10 00 43 52 R 73 Note 1 105 Note 5
11 03, Note 7 44 2D - 74 Note 1 106 Note 5
12 02, Note 8 45 35 5 75 Note 1 107 Note 5
13 00 46 37 7 76 Note 1 108 Note 5
14 00 47 45 E 77 Note 1 109 Note 5
15 00 48 30 0 78 Note 1 110 Note 5
16 C8 49 41, Note 4 A 79 Note 1 111 Note 5
17 C8 50 50, Note 4 P 80 Note 1 112 Note 5
18 00 51 5A, Note 4 Z 81 Note 1 113 Note 5
19 00 52 20, Note 4 82 Note 1 114 Note 5
20 41 A 53 20, Note 4 83 Note 1 115 Note 5
21 56 V 54 20 84 Note 2 116 Note 5
22 41 A 55 20 85 Note 2 117 Note 5
23 47 G 56 30 0 86 Note 2 118 Note 5
24 4F O 57 30 0 87 Note 2 119 Note 5
25 20 58 30 0 88 Note 2 120 Note 5
26 20 59 30 0 89 Note 2 121 Note 5
27 20 60 05 90 Note 2 122 Note 5
28 20 61 1E 91 Note 2 123 Note 5
29 20 62 00 92 00 124 Note 5
30 20 93 00 125 Note 5
31 20 94 00 126 Note 5
32 20 127 Note 5
1. Addresses 68 - 83 specify a unique identier.
2. Addresses 84 - 91 specify the date code.
3. Addresses 63 and 95 are check sums. Address 63 is the check sum for bytes 0 - 62 and address 95 is the check sum for bytes 64 - 94.
4. Part number options LZ, PZ, ALZ, APZ, etc. Example: for AP option, hexes in addresses 49, 50, 51, 52 and 52 will be 41, 50, 5A, 20 and 20
respectively.
5. Addresses 96-127 are vendor specic data.
6. Addresses 5 and 6 specify compliance code. Address 5 with Hex 01 for OC-3 and address 6 with Hex 20 for Fast Ethernet.
7. Address 11 species encoding code. Hex 03 for OC-3 and Hex 02 for Fast Ethernet.
8. Address 12 species bit rate. Hex 02 for OC-3 and Hex 01 for Fast Ethernet.
8
Figure 7. Module Drawing
13.8±0.1
[0.541±0.004]
2.60
[0.10]
55.2±0.2
[2.17±0.01]
13.4±0.1
[0.528±0.004]
AVAGO HFBR-57E0xxZ
YYWW
Country of Origin
DEVICE SHOWN WITH
DUST CAP AND BAIL
WIRE DELATCH
6.25±0.05
[0.246±0.002]
TX RX
DIMENSIONS ARE IN MILLIMETERS (INCHES)
8.5±0.1
[0.335±0.004]
FRONT EDGE OF SFP
TRANSCEIVER CAGE
0.7MAX. UNCOMPRESSED
[0.028]
13.0±0.2
[0.512±0.008]
6.6
[0.261]
13.50
[0.53]
AREA
FOR
PROCESS
PLUG
14.8MAX. UNCOMPRESSED
Tcase Reference Point
9
Figure 8. SFP host board mechanical layout
2x 1.7
20x 0.5 ± 0.03
0.9
2 ± 0.005 TYP.
0.06 L A S B S
10.53
11.93
20
10
11
PIN 1
20
10
11
PIN 1
0.8
TYP.
10.93
9.6
2x 1.55 ± 0.05
3.2
5
LEGEND
1. PADS AND VIAS ARE CHASSIS GROUND
2. THROUGH HOLES, PLATING OPTIONAL
3. HATCHED AREA DENOTES COMPONENT
AND TRACE KEEPOUT (EXCEPT
CHASSIS GROUND)
4. AREA DENOTES COMPONENT
KEEPOUT (TRACES ALLOWED)
DIMENSIONS ARE IN MILLIMETERS
4
3
2
1
1
26.8
5
11x 2.0
10
3x
41.3
42.3
B
10x
1.05 ± 0.01
16.25
REF .
14.25
11.08
8.58
5.68
2.0
11x
11.93
9.6
4.8
8.48
A
3.68
SEE DETAIL 1
9x 0.95 ± 0.05
2.5
7.17.2
2.5
10
3x
34.5
16.25
MIN. PITCH
Y
X
DETAIL 1
0.85 ± 0.05
PCB
EDGE
0.06 L A S B S
0.1 L A S B S
0.1 L X A S
0.1 L X A S
0.1 S X
Y

HFBR-57E0LZ

Mfr. #:
Manufacturer:
Broadcom / Avago
Description:
Fiber Optic Transmitters, Receivers, Transceivers MM LC SFP OC3/FE/TX- DIS STDDL RoHS
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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