AD7650ASTZRL Datasheet AD7650ASTZ, AD7650ASTZRL, AD7650ACPZRL | P13-P15

REV. 0

AD7650

–12–

•

The noise generated by the driver amplifier needs to be kept

as low as possible to preserve the SNR and transition noise

performance of the AD7650. The noise coming from the

driver is filtered by the AD7650 analog input circuit one-pole

low-pass filter made by R1 and C2 or the external filter if any

are used.

•

The driver needs to have a THD performance suitable to that

of the AD7650.

The AD8021 meets these requirements and is usually appropri-

ate for almost all applications. The AD8021 needs an external

compensation capacitor of 10 pF. This capacitor should have

good linearity as an NPO ceramic or mica type.

The AD8022 could also be used where dual version is needed

and gain of 1 is used.

The AD829 is another alternative where high-frequency (above

100 kHz) performance is not required. In gain of 1, it requires

an 82 pF compensation capacitor.

The AD8610 is another option where low bias current is needed

in low-frequency applications.

Voltage Reference Input

The AD7650 uses an external 2.5 V voltage reference. The volt-

age reference input REF of the AD7650 has a dynamic input

impedance. Therefore, it should be driven by a low impedance

source with an efficient decoupling between REF and REFGND

inputs. This decoupling depends on the choice of the voltage

reference, but usually consists of a low ESR tantalum capacitor

connected to the REF and REFGND inputs with minimum para-

sitic inductance. 47 µF is an appropriate value for tantalum capacitor

when used with one of the recommended reference voltages:

•

The low-noise, low temperature drift ADR421 and AD780

voltage references.

•

The low-power ADR291 voltage reference.

•

The low-cost AD1582 voltage reference.

For applications using multiple AD7650s, it is more effective to

buffer the reference voltage with a low-noise, very stable op amp

such as the AD8031.

Care should also be taken with the reference temperature coeffi-

cient of the voltage reference which directly affects the full-scale

accuracy if this parameter matters. For instance, a ± 15 ppm/°C

tempco of the reference changes the full scale by ± 1 LSB/°C.

Note that V

REF

, as mentioned in the specification table, could

be increased to AVDD –1.85 V. Since the input range is defined

in terms of V

REF

, this would essentially increase the range to

make it a 0 V to 3 V input range with a reference voltage of 3 V.

The AD780 can be selected with a 3 V reference voltage.

Power Supply

The AD7650 uses three sets of power supply pins: an analog 5 V

supply AVDD, a digital 5 V core supply DVDD, and a digital

input/output interface supply OVDD. The OVDD supply allows

direct interface with any logic working between 2.7 V and 5.25 V.

To reduce the number of supplies needed, the digital core (DVDD)

can be supplied through a simple RC filter from the analog

supply as shown in Figure 5. The AD7650 is independent of

power supply sequencing and thus free from supply voltage

induced latchup.

Analog Input

Figure 6 shows an equivalent circuit of the input structure of the

AD7650.

IN+

OR IN–

AGND

AV DD

Figure 6. Equivalent Analog Input Circuit

The two diodes, D1 and D2, provide ESD protection for the

analog inputs IN+ and IN–. Care must be taken to ensure that the

analog input signal never exceeds the supply rails by more than

0.3 V. This will cause these diodes to become forward-biased and

start conducting current. These diodes can handle a forward-

biased current of 100 mA maximum. For instance, these conditions

could eventually occur when the input buffer’s (U1) supplies are

different from AVDD. In such case, an input buffer with a short

circuit current limitation can be used to protect the part.

This analog input structure allows the sampling of the differential

signal between IN+ and IN–. Unlike other converters, the IN–

input is sampled at the same time as the IN+ input. By using

this differential input, small signals common to both inputs are

rejected. For instance, by using IN– to sense a remote signal

ground, difference of ground potentials between the sensor and

the local ADC ground are eliminated.

During the acquisition phase, the impedance of the analog input

IN+ can be modeled as a parallel combination of capacitor C1

and the network formed by the series connection of R1 and C2.

Capacitor C1 is primarily the pin capacitance. The resistor R1 is

typically 140 Ω and is a lumped component made up of some

serial resistors and the on resistance of the switches. The capacitor

C2 is typically 60 pF and is mainly the ADC sampling capacitor.

During the conversion phase, where the switches are opened,

the input impedance is limited to C1. The R1, C2 makes a one-

pole low-pass filter that reduces undesirable aliasing effect and

limits the noise.

When the source impedance of the driving circuit is low, the

AD7650 can be driven directly. Large source impedances will

significantly affect the ac performances, especially the total

harmonic distortion.

Driver Amplifier Choice

Although the AD7650 is easy to drive, the driver amplifier needs

to meet at least the following requirements:

•

The driver amplifier and the AD7650 analog input circuit

must be able together to settle for a full-scale step the capacitor

array at a 16-bit level (0.0015%). In the amplifier’s data sheet,

the settling at 0.1% to 0.01% is more commonly specified. It

could significantly differ from the settling time at 16-bit level

and it should therefore be verified prior to the driver selection.

The tiny op amp AD8021, which combines ultralow noise and

a high-gain bandwidth, meets this settling time requirement

even when used with high gain up to 13.

REV. 0

–13–

AD7650

POWER DISSIPATION VS. THROUGHPUT

Operating currents are very low during the acquisition phase,

which allows a significant power saving when the conversion

rate is reduced as shown in Figure 7. This power saving depends

on the mode used. In impulse mode, the AD7650 automatically

reduces its power consumption at the end of each conversion

phase. This feature makes the AD7650 ideal for very low power

battery applications. It should be noted that the digital interface

remains active even during the acquisition phase. To reduce the

operating digital supply currents even further, the digital inputs

need to be driven close to the power supply rails (i.e., DVDD or

DGND for all inputs except EXT/INT, INVSYNC, INVSCLK,

RDC/SDIN, and OVDD or OGND for these last four inputs).

100k

0.1

POWER DISSIPATION – ␮W

SAMPLING RATE – SPS

100k1k101 100 10k 1M

10k

100

0.1

WARP/NORMAL

IMPULSE

Figure 7. Power Dissipation vs. Sampling Rate

CONVERSION CONTROL

Figure 8 shows the detailed timing diagrams of the conversion

process. The AD7650 is controlled by the signal CNVST which

initiates conversion. Once initiated, it cannot be restarted or

aborted, even by the power-down input PD, until the conver-

sion is complete. The CNVST signal operates independently of

CS and RD signals.

CNVST

BUSY

MODE

ACQUIRE CONVERT ACQUIRE CONVERT

Figure 8. Basic Conversion Timing

In impulse mode, conversions can be automatically initiated.

If CNVST is held low when BUSY is low, the AD7650 controls

the acquisition phase and then automatically initiates a new

conversion. By keeping CNVST low, the AD7650 keeps the

conversion process running by itself. It should be noted that the

analog input has to be settled when BUSY goes low. Also, at

power-up, CNVST should be brought low once to initiate the

conversion process. In this mode, the AD7650 could sometimes

run slightly faster then the guaranteed limits in the impulse mode

of 444 kSPS. This feature does not exist in warp or normal modes.

RESET

DATA

BUSY

CNVST

Figure 9. RESET Timing

Although CNVST is a digital signal, it should be designed with

special care with fast, clean edges, and levels with minimum

overshoot and undershoot or ringing.

It is a good thing to shield the CNVST trace with ground and

also to add a low value serial resistor (i.e., 50 V) termination

close to the output of the component that drives this line.

For applications where the SNR is critical, CNVST signal should

have a very low jitter. Some solutions to achieve that is to use a

dedicated oscillator for CNVST generation or, at least, to clock

it with a high-frequency low-jitter clock as shown in Figure 5.

DIGITAL INTERFACE

The AD7650 has a versatile digital interface; it can be interfaced

with the host system by using either a serial or parallel interface.

The serial interface is multiplexed on the parallel data bus. The

AD7650 digital interface also accommodates both 3 V or 5 V logic

by simply connecting the OVDD supply pin of the AD7650 to

the host system interface digital supply. Finally, by using the

OB/2C input pin, both two’s complement or straight binary

coding can be used.

The two signals CS and RD control the interface. When at least

one of these signals is high, the interface outputs are in high

impedance. Usually, CS allows the selection of each AD7650 in

multicircuits applications and is held low in a single AD7650

design. RD is generally used to enable the conversion result on

the data bus.

CNVST

BUSY

DATA

BUS

CS = RD = 0

PREVIOUS CONVERSION DATA NEW DATA

Figure 10. Master Parallel Data Timing for Reading

(Continuous Read)

REV. 0

AD7650

–14–

CONVERSION

CS = 0

CNVST,

BUSY

DATA

BUS

Figure 12. Slave Parallel Data Timing for Reading

(Read During Convert)

SERIAL INTERFACE

The AD7650 is configured to use the serial interface when the

SER/PAR is held high. The AD7650 outputs 16 bits of data,

MSB first, on the SDOUT pin. This data is synchronized with

the 16 clock pulses provided on SCLK pin. The output data is

valid on both the rising and falling edge of the data clock.

MASTER SERIAL INTERFACE

Internal Clock

The AD7650 is configured to generate and provide the serial data

clock SCLK when the EXT/

INT

pin is held low. The AD7650

also generates a SYNC signal to indicate to the host when the

serial data is valid. The serial clock SCLK and the SYNC signal

can be inverted if desired. Depending on RDC/SDIN input, the

data can be read after each conversion or during the following

conversion. Figure 13 and Figure 14 show the detailed timing

diagrams of these two modes.

PARALLEL INTERFACE

The AD7650 is configured to use the parallel interface when the

SER/PAR is held low. The data can be read either after each

conversion, which is during the next acquisition phase, or dur-

ing the following conversion as shown, respectively, in Figure 11

and Figure 12. When the data is read during the conversion,

however, it is recommended that it is read only during the first

half of the conversion phase. That avoids any potential feed-

through between voltage transients on the digital interface and

the most critical analog conversion circuitry.

CURRENT

CONVERSION

BUSY

DATA

BUS

Figure 11. Slave Parallel Data Timing for Reading

(Read After Convert)

BUSY

CS, RD

CNVST

SYNC

SCLK

SDOUT

123 141516

D15 D14 D2 D1 D0

EXT/INT = 0 RDC/SDIN = 0 INVSCLK = INVSYNC = 0

Figure 13. Master Serial Data Timing for Reading (Read After Convert)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21

AD7650ASTZRL

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Manufacturer:

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Description:

Analog to Digital Converters - ADC 16B 570kSPS Unipolar CMOS Success Approx

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AD7650ASTZRL

AD7650ASTZRL

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