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AD7650ASTZRL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
REV. 0
–3–
AD7650
TIMING SPECIFICATIONS
Parameter Symbol Min Typ Max Unit
REFER TO FIGURES 8 AND 9
Convert Pulsewidth t
1
5ns
Time Between Conversions t
2
1.75/2/2.25 Note 1 µs
(Warp Mode/Normal Mode/Impulse Mode)
CNVST LOW to BUSY HIGH Delay t
3
30 ns
BUSY HIGH All Modes Except in t
4
1.5/1.75/2 µs
Master Serial Read After Convert Mode
(Warp Mode/Normal Mode/Impulse Mode)
Aperture Delay t
5
2ns
End of Conversion to BUSY LOW Delay t
6
10 ns
Conversion Time t
7
1.5/1.75/2 µs
(Warp Mode/Normal Mode/Impulse Mode)
Acquisition Time t
8
250 ns
RESET Pulsewidth t
9
10 ns
REFER TO FIGURES 10, 11 AND 12
(Parallel Interface Modes)
CNVST LOW to DATA Valid Delay t
10
1.5/1.75/2 µs
(Warp Mode/Normal Mode/Impulse Mode)
DATA Valid to BUSY LOW Delay t
11
45 ns
Bus Access Request to DATA Valid t
12
40 ns
Bus Relinquish Time t
13
515ns
REFER TO FIGURES 13 AND 14
(Master Serial Interface Modes)
2
CS LOW to SYNC Valid Delay t
14
10 ns
CS LOW to Internal SCLK Valid Delay
2
t
15
10 ns
CS LOW to SDOUT Delay t
16
10 ns
CNVST LOW to SYNC Delay t
17
25/275/525 ns
(Warp Mode/Normal Mode/Impulse Mode)
SYNC Asserted to SCLK First Edge Delay t
18
4ns
Internal SCLK Period t
19
40 75 ns
Internal SCLK HIGH (INVSCLK Low)
3
t
20
30 ns
Internal SCLK LOW (INVSCLK Low)
3
t
21
9.5 ns
SDOUT Valid Setup Time t
22
4.5 ns
SDOUT Valid Hold Time t
23
3ns
Parameter Condition Min Typ Max Unit
POWER SUPPLIES (continued)
Operating Current
5
570 kSPS Throughput
AVDD 15.5 mA
DVDD
6
4.2 mA
OVDD
6
100 µA
Power Dissipation
6
570 kSPS Throughput
5
115 mW
444 kSPS Throughput
7
77 mW
100 SPS Throughput
7
21 µW
In Power-Down Mode
8
7 µW
TEMPERATURE RANGE
9
Specified Performance T
MIN
to T
MAX
–40 +85 °C
NOTES
1
LSB means Least Significant Bit. With the 0 V to 2.5 V input range, one LSB is 38.15 µV.
2
See Definition of Specifications section. These specifications do not include the error contribution from the external reference.
3
Tested in warp mode.
4
All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale unless otherwise specified.
5
In warp mode.
6
Tested in parallel reading mode.
7
In impulse mode.
8
With all digital inputs forced to OVDD or OGND respectively.
9
Contact factory for extended temperature range.
Specifications subject to change without notice.
(–40ⴗC to +85ⴗC, AVDD = DVDD
= 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
REV. 0
–3–
AD7650
REV. 0
AD7650
–4–
TIMING SPECIFICATIONS
Parameter Symbol Min Typ Max Unit
REFER TO FIGURES 13 AND 14 (continued)
SCLK Last Edge to SYNC Delay t
24
3
CS HIGH to SYNC HI-Z t
25
10 ns
CS HIGH to Internal SCLK HI-Z t
26
10 ns
CS HIGH to SDOUT HI-Z t
27
10 ns
BUSY HIGH in Master Serial Read After Convert t
28
2.75/3/3.25 µs
(Warp Mode/Normal Mode/Impulse Mode)
CNVST LOW to SYNC Asserted Delay t
29
1/1.25/1.5 µs
(Warp Mode/Normal Mode/Impulse Mode)
SYNC Deasserted to BUSY LOW Delay t
30
50 ns
REFER TO FIGURES 15 AND 16
(Slave Serial Interface Modes)
2
External SCLK Setup Time t
31
5ns
External SCLK Active Edge to SDOUT Delay t
32
316ns
SDIN Setup Time t
33
5ns
SDIN Hold Time t
34
5ns
External SCLK Period t
35
25 ns
External SCLK HIGH t
36
10 ns
External SCLK LOW t
37
10 ns
NOTES
1
In warp mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time.
2
In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C
L
of 10 pF; otherwise, the load is 60 pF maximum.
3
If the polarity of SCLK is inverted, the timing references of SCLK are also inverted.
Specifications subject to change without notice.
(continued)
I
OH
500␮A
1.6mA
I
OL
TO OUTPUT
PIN
1.4V
C
L
60pF*
*IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD
C
L
OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
Figure 1. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, SCLK Outputs, C
L
= 10 pF
0.8V
2V
2V
0.8V
0.8V
2V
t
DELAY
t
DELAY
Figure 2. Voltage Reference Levels for Timing
REV. 0
–5–
AD7650
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD7650AST –40°C to +85°C Quad Flatpack (LQFP) ST-48
AD7650ASTRL –40°C to +85°C Quad Flatpack (LQFP) ST-48
AD7650ACP
1
–40°C to +85°C Quad Flatpack (LFCSP) CP-48
1
AD7650ACPRL
1
–40°C to +85°C Quad Flatpack (LFCSP) CP-48
1
EVAL-AD7650CB
2
Evaluation Board
EVAL-CONTROL BRD2
3
Controller Board
NOTES
1
Future Product. Contact Factory for availability.
2
This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes.
3
This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designator.
ABSOLUTE MAXIMUM RATINGS
1
Analog Inputs
IN+
2
, REF, IN–, REFGND . . . . . . . . . . . . AVDD + 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . to AGND – 0.3 V
Ground Voltage Differences
AGND, DGND, OGND . . . . . . . . . . . . . . . . . . . . ± 0.3 V
Supply Voltages
AVDD, DVDD, OVDD . . . . . . . . . . . . . . . . . . . . . . . 7 V
AVDD to DVDD,
AVDD to OVDD . . . . . . . . . . . . . ± 7 V
DVDD to OVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 7 V
Digital Inputs
Except the Data Bus D(7:4) . . . . –0.3 V to DVDD + 0.3 V
Data Bus Inputs D(7:4) . . . . . . . –0.3 V to OVDD + 0.3 V
Internal Power Dissipation
3
. . . . . . . . . . . . . . . . . . . 700 mW
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range
(Soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
See Analog Input section.
3
Specification is for device in free air:
48-Lead LQFP: θ
JA
= 91°C/W, θ
JC
= 30°C/W.
48-Lead LFCSP: θ
JC
= 26°C/W.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7650 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

AD7650ASTZRL

Mfr. #:
Buy AD7650ASTZRL
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 16B 570kSPS Unipolar CMOS Success Approx
Lifecycle:
New from this manufacturer.
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