RT8228A
10
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Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
Application Information
The RT8228A PWM controller provides high efficiency,
excellent transient response, and high DC output accuracy
needed for stepping down high voltage batteries to
generate low voltage CPU core, I/O, and chipset RAM
supplies in notebook computers. Richtek Mach
Response
TM
technology is specifically designed for
providing 100ns instant-on response to load steps while
maintaining a relatively constant operating frequency and
inductor operating point over a wide range of input voltages.
The topology circumvents the poor load transient timing
problems of fixed frequency current mode PWMs while
avoiding the problems caused by widely varying switching
frequencies in conventional constant on-time and constant
off-time PWM schemes. The PSR PWM modulator is
specifically designed to have better noise immunity for
such a single output application.
PWM Operation
The Mach Response
TM
, PSR (Pulse Shaping Regulator)
mode controller is suitable for low external component
count configuration with appropriate amount of Equivalent
Series Resistance (ESR) capacitor(s) at the output. The
output ripple valley voltage is monitored at a feedback
point voltage. Refer to the function diagrams of the
RT8228A, the synchronous high side MOSFET is turned
on at the beginning of each cycle. After the internal one-
shot timer expires, the MOSFET is turned off. The pulse
width of this one shot is determined by the converter's
input and output voltages to keep the frequency fairly
constant over the entire input voltage range. Another one-
shot sets a minimum off-time (400ns typ.).
On-Time Control
The on-time one-shot comparator has two inputs. One
input looks at the output voltage, while the other input
samples the input voltage and converts it to a current.
This input voltage proportional current is used to charge
an internal on-time capacitor. The on-time is the time
required for the voltage on this capacitor to charge from
zero volts to VOUT, thereby making the on-time of the
high side switch directly proportional to the output voltage
and inversely proportional to the input voltage. The
implementation results in a nearly constant switching
frequency without the need of a clock generator.
Mode Selection Operation
DEM (Diode Emulation Mode) and ASM (Audio Skipping
Mode) operation can be enabled by driving the tri-state
MODE pin to a logic high level. The RT8228A can switch
operation into DEM when the MODE pin is pulled up to
5V. If MODE is pulled to 2.5V, the controller will switch
operation into ASM. Finally, if the pin is pulled to GND,
the RT8228A will operate in CCM mode.
Diode Emulation Mode
In diode emulation mode, the RT8228A automatically
reduces switching frequency at light load conditions to
maintain high efficiency. This reduction of frequency is
achieved smoothly and without increasing VOUT ripple or
load regulation. As the output current decreases from heavy
load condition, the inductor current is also reduced, and
eventually comes to the point that its valley touches zero
current, which is the boundary between continuous
conduction and discontinuous conduction modes. By
emulating the behavior of diodes, the low side MOSFET
allows only partial of negative current when the inductor
freewheeling current reach negative. As the load current
is further decreased, it takes longer and longer to discharge
the output capacitor to the level than requires the next
ON cycle. The on-time is kept the same as that in the
heavy load condition. In reverse, when the output current
increases from light load to heavy load, the switching
frequency increases to the preset value as the inductor
current reaches the continuous condition. The transition
load point to the light load operation can be calculated as
follows (Figure 1) :
(
)
≈×
IN OUT
LOAD ON
VV
It
2L
×
OUT
IN
ON
V
Frequency =
Vt
where R
TON
is the resistor connected from the input supply
(V
IN
) to the TON pin.
And then the switching frequency is :
××
+
TON OUT
ON
IN
7.06p R V
t = 33ns
(V 0.9)
where t
ON
is On-time.
RT8228A
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Figure 1. Boundary Condition of CCM/DEM
The switching waveforms may appear noisy and
asynchronous when light loading causes diode emulation
operation, but this is a normal operating condition that
results in high light load efficiency. Trade offs in DEM
noise vs. light load efficiency is made by varying the
inductor value. Generally, low inductor values produce a
broader efficiency vs. load curve, while higher values result
in higher full load efficiency (assuming that the coil
resistance remains fixed) and less output voltage ripple.
The disadvantages for using higher inductor values include
larger physical size and degrade load transient response
(especially at low input voltage levels).
Audio Skipping Mode
When the MODE pin is pulled to 2.5V, the controller
operates in audio skipping mode with a minimum switching
frequency of 25kHz. This mode eliminates audio frequency
modulation that would otherwise be present when a lightly
loaded controller automatically skips pulses. In audio
skipping mode, the low side switch gate driver signal is
ORed with an internal oscillator (>25kHz). Once the
internal oscillator is triggered, the audio skipping controller
pulls LGATE logic high, turning on the low side MOSFET
to induce a negative inductor current. After the output
voltage rises above V
REF
, the controller turns off the low
side MOSFET (LGATE pulled logic low) and triggers a
constant on-time operation (UGATE driven logic high).
When the on-time operation expires, the controller re-
enables the low side MOSFET until the inductor current
drops below the zero crossing threshold.
Forced-CCM Mode
The low noise, forced-CCM mode (MODE = GND) disables
the zero-crossing comparator, which controls the low side
switch on-time. This causes the low side gate drive
waveform to become the complement of the high side
gate drive waveform. This in turn causes the inductor
current to reverse at light loads as the PWM loop to
maintain a duty ratio V
OUT
/V
IN
. The benefit of forced-CCM
mode is to keep the switching frequency fairly constant,
but it comes at a cost. The no load battery current can be
up to 10mA to 40mA, depending on the external
MOSFETs.
Current Limit Setting (OCP)
The RT8228A has cycle-by-cycle current limiting control.
The current limit circuit employs a unique valley current
sensing algorithm. If PHASE voltage plus the current limit
threshold is below zero, the PWM is not allowed to initiate
a new cycle (Figure 2). In order to provide both good
accuracy and a cost effective solution, the RT8228A
supports temperature compensated MOSFET R
DS(ON)
sensing. The CS pin should be connected to GND through
the trip voltage setting resistor, R
CS
. With the 10μA CS
terminal source current, I
CS
, and the setting resistor, R
CS
the CS trip voltage, V
CS
, can be calculated as shown in
the following equation.
V
CS
(mV) = R
CS
(kΩ) x 10 (μA) x (1 / 10)
Inductor current is monitored by the voltage between the
PGND pin and the PHASE pin, so the PHASE pin should
be connected to the drain terminal of the low side
MOSFET. I
CS
has positive temperature coefficient to
compensate the temperature dependency of the R
DS(ON)
.
PGND is used as the positive current sensing node so
PGND should be connected to the source terminal of the
bottom MOSFET.
As the comparison is done during the OFF state, V
CS
sets the valley level of the inductor current. Thus, the
load current at over current threshold, I
LOAD_OC
, can be
calculated as follows.
I
L
t
0
t
ON
Slope = (V
IN
-V
OUT
) / L
I
PEAK
I
LOAD
= I
PEAK
/ 2
()
−×
×
×
CS Ripple
LOAD_OC
DS(ON)
IN OUT OUT
CS
DS(ON) IN
VI
I = +
R2
VV V
V
1
= +
R2 x Lf V
RT8228A
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Figure 3. Reducing the UGATE Rise Time
BOOT
UGATE
PHASE
V
IN
Power Good Output (PGOOD)
The power good output is an open drain output and requires
a pull-up resistor. When the output voltage is 25% above
or 10% below its set voltage, PGOOD gets pulled low. It
is held low until the output voltage returns to within these
tolerances once more. In soft-start, PGOOD is actively
held low and is allowed to transition high until soft-start is
over and the output reaches 93% of its set voltage. There
is a 2.5μs delay built into PGOOD circuitry to prevent
false transitions.
POR, UVLO and Soft-Start
Power On Reset (POR) occurs when VCC rises above to
approximately 3.9V, the RT8228A will reset the fault latch
and preparing the PWM for operation. Below 3.7V, the
VCC Under Voltage Lockout (UVLO) circuitry inhibits
switching by keeping UGATE and LGATE low. A built-in
soft-start is used to prevent surge current from power supply
input after EN is enabled. A current ramping up limit
threshold can eliminate the V
OUT
folded-back in the soft-
start duration. The typical soft-start duration is 900μs.
Output Over Voltage Protection (OVP)
The output voltage can be continuously monitored for over
voltage protection. When the output voltage exceeds 25%
of the set voltage threshold, over voltage protection is
triggered and the low side MOSFET is latched on. This
activates the low side MOSFET to discharge the output
capacitor. The RT8228A is latched once OVP is triggered
and can only be released by VCC or EN power on reset.
There is a 5μs delay built into the over voltage protection
circuit to prevent false transitions.
Output Under Voltage Protection (UVP)
The output voltage can be continuously monitored for under
voltage protection. When the output voltage is less than
70% of the set voltage threshold, under voltage protection
is triggered and then both UGATE and LGATE gate drivers
are forced low. During soft-start, the UVP blanking time is
4.5ms.
Output Voltage Setting (FB)
The output voltage can be adjusted from 0.5V to 3.3V by
setting the feedback resistor R1 and R2 (Figure 4). Choose
Figure 2. Valley Current Limit
I
L
t
0
I
LIM
I
PEAK
I
LOAD
MOSFET Gate Driver (UGATE, LGATE)
The high side driver is designed to drive high current, low
R
DS(ON)
N-MOSFET (s). When configured as a floating
driver, 5V bias voltage is delivered from the VDDP supply.
The average drive current is proportional to the gate charge
at V
GS
= 5V times switching frequency. The instantaneous
drive current is supplied by the flying capacitor between
BOOT and PHASE pins. A dead time to prevent shoot
through is internally generated between high side
MOSFET off to low side MOSFET on and low side
MOSFET off to high side MOSFET on. The low side driver
is designed to drive high current, low R
DS(ON)
N-MOSFET (s).
The internal pull down transistor that drives LGATE low is
robust, with a 0.8Ω typical on resistance. A 5V bias voltage
is delivered from the VDDP supply. The instantaneous drive
current is supplied by the flying capacitor between VDDP
and GND.
For high current applications, some combinations of high
and low side MOSFETs might be encountered that will
cause excessive gate drain coupling, which can lead to
efficiency killing, EMI-producing shoot through currents.
This is often remedied by adding a resistor in series with
BOOT, which increases the turn-on time of the high side
MOSFET without degrading the turn-off time (Figure 3).

RT8228AZQW

Mfr. #:
Manufacturer:
Description:
IC REG CTRLR BUCK 12WQFN
Lifecycle:
New from this manufacturer.
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