RT8228A
13
RT8228A-06 January 2014 www.richtek.com
©
Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
⎛⎞
×
⎜⎟
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OUT REF
R1
V = V 1+
R2
where V
REF
is 0.5V.(typ.)
Figure 4. Setting VOUT with a Resistor Divider
Output Inductor Selection
The switching frequency (on-time) and operating point (%
ripple or LIR) determine the inductor value as follows :
(
×−
×
ON IN OUT
IR LOAD(MAX)
TVV
L =
LI
R2 to be approximately 10kΩ, and solve for R1 using the
equation :
where L
IR
is the ratio of peak-of-peak ripple current to the
maximum average inductor current. Find a low pass
inductor having the lowest possible DC resistance that
fits in the allowed dimensions. Ferrite cores are often the
best choice, although powdered iron is inexpensive and
can work well at 200kHz. The core must be large enough
and not to saturate at the peak inductor current (I
PEAK
) :
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⎛⎞
×
⎢⎥
⎜⎟
⎝⎠
⎣⎦
IR
PEAK LOAD(MAX) LOAD(MAX)
L
I = I + I
2
Output Capacitor Selection
The output filter capacitor must have low enough Equivalent
Series Resistance (ESR) to meet output ripple and load-
transient requirements, yet have high enough ESR to
satisfy stability requirements. The output capacitance
must also be high enough to absorb the inductor energy
while transitioning from full-load to no-load conditions
without tripping the overvoltage fault latch.
Although Mach Response
TM
DRV
TM
dual ramp valley mode
provides many advantages such as ease-of-use, minimum
external component configuration, and extremely short
response time, due to not employing an error amplifier in
the loop, a sufficient feedback signal needs to be provided
by an external circuit to reduce the jitter level. The required
signal level is approximately 15 mV at the comparing point.
This generates V
RIPPLE
= (V
OUT
/ 0.5) x 15mV at the output
node. The output capacitor ESR should meet this
requirement.
Thermal Considerations
For continuous operation, do not exceed absolute
maximum operation junction temperature. The maximum
power dissipation depends on the thermal resistance of
IC package, PCB layout, the rate of surroundings airflow
and temperature difference between junction to ambient.
The maximum power dissipation can be calculated by
following formula :
P
D(MAX)
= (T
J(MAX)
− T
A
) / θ
JA
where T
J(MAX)
is the maximum operation junction
temperature 125°C, T
A
is the ambient temperature and
the θ
JA
is the junction to ambient thermal resistance.
For recommended operating conditions specification of
RT8228A, the maximum junction temperature is 125°C
and T
A
is the ambient temperature. The junction to ambient
thermal resistance, θ
JA
, is layout dependent. For WQFN-
12L 2x2 package, the thermal resistance, θ
JA
, is 165°C/
W on a standard JEDEC 51-3 single-layer thermal test
board. The maximum power dissipation at T
A
= 25°C can
be calculated by the following formula :
P
D(MAX)
= (125°C − 25°C) / (165°CW) = 0.606W for
WQFN-12L 2x2 package
The maximum power dissipation depends on the operating
ambient temperature for fixed T
J(MAX)
and thermal
resistance, θ
JA
. For the RT8228A package, the derating
curve in Figure 5 allows the designer to see the effect of
rising ambient temperature on the maximum power
dissipation.
PHASE
LGATE
R1
R2
V
OUT
V
IN
UGATE
FB
GND
