MAX7042ATJ+T Datasheet MAX7042ATJ+, MAX7042ATJ+T | P13-P15

MAX7042

308MHz/315MHz/418MHz/433.92MHz

Low-Power, FSK Superheterodyne Receiver

______________________________________________________________________________________ 13

Data Filters

The data filter is implemented as a 2nd-order lowpass

Sallen-Key filter. The pole locations are set by the com-

bination of two on-chip resistors and two external

capacitors. Adjusting the value of the external capaci-

tors changes the corner frequency to optimize for dif-

ferent data rates. The corner frequency in kHz should

be to approximately the fastest expected data rate in

kbps for NRZ and twice the fastest expected data rate

in kbps for Manchester coding from the transmitter.

Keeping the corner frequency near the data rate

rejects any noise at higher frequencies, resulting in an

increase in receiver sensitivity.

The configuration shown in Figure 2 creates a Butterworth

or Bessel response. The Butterworth filter offers a very

flat amplitude response in the passband and a rolloff rate

of 40dB/decade for the two-pole filter. The Bessel filter

has a linear phase response, which works well for filter-

ing digital data. To calculate the value of the capacitors,

use the following equations along with the coefficients in

Table 2:

where f

is the desired 3dB corner frequency.

For example, choose a Butterworth filter response with

a 5kHz corner frequency:

Choosing standard capacitor values changes C

470pF and C

to 220pF. In the

Typical Application

Circuit

, C

and C

are named C4 and C3, respectively.

Data Slicer

The purpose of a data slicer is to take the analog output

of a data filter and convert it to a digital signal. This is

achieved by using a comparator and comparing the ana-

log input to a threshold voltage. The threshold voltage is

set by the voltage on the DS- pin, which is connected to

the negative input of the data-slicer comparator. The pos-

itive input of the data-slicer comparator is connected to

the output of the data filter internally.

k kHz

1 000

1 414 100 3 14 5

450

1 414

4 100 3 14 5

225

( . )( )( . )( )

( )( )( . )( )

=≈

Ω

ak f

100

4 100

()()()

Ω

Table 2. Coefficients to Calculate C

and

FILTER TYPE a b

Butterworth

(Q = 0.707)

1.414 1.000

Bessel

(Q = 0.577)

1.3617 0.618

FSK DEMOD

100kΩ

DS+ OP+

100kΩ

MAX7042

Figure 2. Sallen-Key Lowpass Data Filter

MAX7042

308MHz/315MHz/418MHz/433.92MHz

Low-Power, FSK Superheterodyne Receiver

14 ______________________________________________________________________________________

Numerous configurations can be used to generate the

data-slicer threshold. For example, the circuit in Figure 3

shows a simple method using only one resistor and one

capacitor. This configuration averages the analog out-

put of the filter and sets the threshold to approximately

50% of that amplitude. With this configuration, the

threshold automatically adjusts as the analog signal

varies, minimizing the possibility for errors in the digital

data. The values of R and C affect how fast the thresh-

old tracks the analog amplitude. Be sure to keep the

corner frequency of the RC circuit much lower than the

lowest expected data rate.

With this configuration, a long string of zeros or ones

can cause the threshold to drift. This configuration

works best if a coding scheme, such as Manchester

coding, which has an equal number of zeros and ones,

is used.

Figure 4 shows a configuration that uses the positive and

negative peak detectors to generate the threshold. This

configuration sets the threshold to the midpoint between

a high output and a low output of the data filter.

Peak Detectors

The maximum peak detector (PDMAX) and minimum

peak detector (PDMIN) outputs, in conjunction with a

resistor and capacitor connected to GND, create DC

output voltages proportional to the high- and low-peak

values of the data signal. The resistor provides a path

for the capacitor to discharge, allowing the peak detec-

tor to dynamically follow peak changes of the data-filter

output voltage.

The positive and negative peak detectors can be used

together to form a data-slicer threshold voltage at a

midvalue between the most positive and most negative

voltage levels of the data stream (see the

Data Slicers

section and Figure 4). Set the RC time constant of the

peak-detector combining network to at least 5 times the

data period.

The MAX7042 peak detectors track the baseband filter

output voltage until all internal circuits are stable follow-

ing an enable pin low-to-high transition. This feature

allows for an extremely fast startup because the peak

detectors never “catch” a false level created by a startup

transient. The peak detectors exhibit a fast-attack/slow-

decay response.

Power-Supply Connections

The MAX7042 can be powered from a 2.4V to 3.6V

supply or a 4.5V to 5.5V supply. The device has an on-

chip linear regulator that reduces the 5V supply to 3V

needed to operate the chip.

To operate the MAX7042 from a 3V supply, connect

DVDD, AVDD, and HVIN to the 3V supply. When using

a 5V supply, connect the supply to HVIN only, and con-

nect AVDD to DVDD. In both cases, bypass DVDD and

HVIN with a 0.01µF capacitor and AVDD with a 0.1µF

capacitor. Place all bypass capacitors as close to the

respective supply pin as possible.

Control Interface Considerations

When operating the MAX7042 with a +4.5V to +5.5V

supply voltage, the LNASEL, FSEL1, FSEL2, and EN

pins can be driven by a microcontroller with either 3V

or 5V interface logic levels. When operating the

MAX7042 with a +2.4V to +3.6V supply, the microcon-

troller must produce logic levels tha conform to the V

and V

specifications in the

DC Electrical

Characteristics Table

DATA DS-

DS+

DATA

SLICER

MAX7042

Figure 3. Generating Data-Slicer Threshold

DATA PDMAX PDMIN

MAX7042

DATA

SLICER

PEAK

DET

PEAK

DET

Figure 4. Generating Data-Slicer Threshold Using the Peak

Detectors

MAX7042

Layout Considerations

A properly designed PCB is an essential part of any

RF/microwave circuit. On high-frequency inputs and

outputs, use controlled-impedance lines and keep

them as short as possible to minimize losses and radia-

tion. At high frequencies, trace lengths that are on the

order of λ/10 or longer act as antennas.

Keeping the traces short also reduces parasitic induc-

tance. Generally, 1in of a PCB trace adds about 20nH

of parasitic inductance. The parasitic inductance can

have a dramatic effect on the effective inductance of a

passive component. For example, a 0.5in trace con-

necting a 100nH inductor adds an extra 10nH of induc-

tance or 10%.

To reduce the parasitic inductance, use wider traces

and a solid ground or power plane below the signal

traces. Also, use low-inductance connections to ground

on all GND pins, and place decoupling capacitors

close to all power-supply connections.

308MHz/315MHz/418MHz/433.92MHz

Low-Power, FSK Superheterodyne Receiver

______________________________________________________________________________________ 15

31 30 29 28 27 26

910 11 12 1314 15

C13

C14

C15

C16

RF INPUT

RSSI

XTAL2

XTAL1

AVDD

LNAIN

3.0V

LNASEL

DATA

HVIN

FSEL2

FSEL1

LNASEL

DATA

FSEL2

FSEL1

DVDD

DGND

OP+

DS+

DS-

PDMAX

PDMIN

IFIN-

AGND

IFIN+

MIXOUT

MIXIN-

EXPOSED PAD

MIXIN+

LNAOUT

LNASRC

GND

OUTIN

C10

C12

C11 C8

RSSI

C2C1

MAX7042

Typical Application Circuit

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

MAX7042ATJ+T

Mfr. #:

Buy MAX7042ATJ+T

Manufacturer:

Maxim Integrated

Description:

RF Receiver 308/315/418/433.9MHz FSK Superhtrdyne Rec

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

MAX7042ATJ+T

MAX7042ATJ+T

Products related to this Datasheet