MAX5842LEUB+ Datasheet MAX5842LEUB+, MAX5842MEUB+, MAX5842MEUB+T | P10-P12

MAX5842

Quad, 12-Bit, Low-Power, 2-Wire, Serial

Voltage-Output DAC

10 ______________________________________________________________________________________

read operations require S

conditions because of the

change in direction of data flow.

Acknowledge Bit (ACK)

The acknowledge bit (ACK) is the ninth bit attached to

any 8-bit data word. ACK is always generated by the

receiving device. The MAX5842 generates an ACK

when receiving an address or data by pulling SDA low

during the ninth clock period. When transmitting data,

the MAX5842 waits for the receiving device to generate

an ACK. Monitoring ACK allows for detection of unsuc-

cessful data transfers. An unsuccessful data transfer

occurs if a receiving device is busy or if a system fault

has occurred. In the event of an unsuccessful data

transfer, the bus master should reattempt communica-

tion at a later time.

Slave Address

A bus master initiates communication with a slave

device by issuing a START condition followed by the

7-bit slave address (Figure 4). When idle, the MAX5842

waits for a START condition followed by its slave

address. The serial interface compares each address

value bit by bit, allowing the interface to power down

immediately if an incorrect address is detected. The

LSB of the address word is the Read/Write (R/W) bit.

R/W indicates whether the master is writing to or read-

ing from the MAX5842 (R/W = 0 selects the write condi-

tion, R/W = 1 selects the read condition). After

receiving the proper address, the MAX5842 issues an

ACK by pulling SDA low for one clock cycle.

The MAX5842 has four different factory/user-pro-

grammed addresses (Table 2). Address bits A6

through A1 are preset, while A0 is controlled by ADD.

Connecting ADD to GND sets A0 = 0. Connecting ADD

to V

sets A0 = 1. This feature allows up to four

MAX5842s to share the same bus.

Write Data Format

In write mode (R/W = 0), data that follows the address

byte controls the MAX5842 (Figure 5). Bits C3-C0 con-

figure the MAX5842 (Table 3). Bits D11-D0 are DAC

data. Input and DAC registers update on the falling

edge of SCL during the acknowledge bit. Should the

write cycle be prematurely aborted, data is not updated

and the write cycle must be repeated. Figure 6 shows

two example write data sequences.

Extended Command Mode

The MAX5842 features an extended command mode

that is accessed by setting C3-C0 = 1 and D11-D8 = 0.

The next data byte writes to the shutdown registers

(Figure 7). Setting bits A, B, C, or D to 1 sets that DAC

SCL

SDA

Figure 2. START and STOP Conditions

SCL

SDA

STOP START

SCL

SDA

ILLEGAL

STOP

START

ILLEGAL EARLY STOP CONDITION

LEGAL STOP CONDITION

Figure 3. Early STOP Conditions

S A6A5A4A3A2A1A0R/W

Figure 4. Slave Address Byte Definition

C3 C2 C1 C0 D11 D10 D9 D8

Figure 5. Command Byte Definition

PART V

ADD

DEVICE ADDRESS

(A6...A0)

MAX5842L GND 0111 100

MAX5842L V

0111 101

MAX5842M GND 1011 100

MAX5842M V

1011 101

Table 2. MAX5842 I

C Slave Addresses

MAX5842

Quad, 12-Bit, Low-Power, 2-Wire, Serial

Voltage-Output DAC

______________________________________________________________________________________ 11

to the selected power-down mode based on the states

of PD0 and PD1 (Table 1). Any combination of the four

DACs can be controlled with a single write sequence.

Read Data Format

In read mode (R/W = 1), the MAX5842 writes the con-

tents of the DAC register to the bus. The direction of

data flow reverses following the address acknowledge

by the MAX5842. The device transmits the first byte of

data, waits for the master to acknowledge, then trans-

mits the second byte. Figure 8 shows an example read

data sequence.

C Compatibility

The MAX5842 is compatible with existing I

C systems.

SCL and SDA are high-impedance inputs; SDA has an

open drain that pulls the data line low during the ninth

clock pulse. The Typical Operating Circuit shows a typ-

ical I

C application. The communication protocol sup-

ports the standard I

C 8-bit communications. The

general call address is ignored. The MAX5842 address

is compatible with the 7-bit I

C addressing protocol

only. No 10-bit address formats are supported.

Digital Feedthrough Suppression

When the MAX5842 detects an address mismatch, the

serial interface disconnects the SCL signal from the

core circuitry. This minimizes digital feedthrough

caused by the SCL signal on a static output. The serial

interface reconnects the SCL signal once a valid

START condition is detected.

Applications Information

Digital Inputs and Interface Logic

The MAX5842 2-wire digital interface is I

C/SMBus

compatible. The two digital inputs (SCL and SDA) load

the digital input serially into the DAC. Schmitt-trigger

buffered inputs allow slow-transition interfaces such as

optocouplers to interface directly to the device. The

digital inputs are compatible with CMOS logic levels.

Power-Supply Bypassing and

Ground Management

Careful PC board layout is important for optimal system

performance. Keep analog and digital signals separate

to reduce noise injection and digital feedthrough. Use a

ground plane to ensure that the ground return from

GND to the power-supply ground is short and low

impedance. Bypass V

with a 0.1µF capacitor to

ground as close to the device as possible.

Chip Information

TRANSISTOR COUNT: 17,213

PROCESS: BiCMOS

MSB

A6 A5 A4 A3 A2 A1 A0 C3 C2 C1 C0 D11 D10 D9 D8

D7 D6 D5 D4 D3 D2 D1 D0 P

R/W ACK

ACK

LSB MSB LSB

EXAMPLE WRITE DATA SEQUENCE

EXAMPLE WRITE TO POWER-DOWN REGISTER SEQUENCE

LSB

MSB

A6 A5 A4 A3 A2 A1 A0 C3 C2 C1 C0 D11 D10 D9 D8

X X D C B A PD1 PD0 P

R/W ACK

ACK

LSB MSB LSB

LSB

Figure 6. Example Write Command Sequences

X X D C B A PD1 PD0

Figure 7. Extended Command Byte Definition

MAX5842

Quad, 12-Bit, Low-Power, 2-Wire, Serial

Voltage-Output DAC

12 ______________________________________________________________________________________

SERIAL DATA INPUT

C3 C2 C1 C0 D11 D10 D9 D8

FUNCTION

0000

DAC

DATA

DAC

DATA

DAC

DATA

DAC

DATA

Load DAC A input and DAC registers with new data.

Contents of DAC B, C, and D input registers are transferred

to the respective DAC registers. All outputs are updated.

0001

DAC

DATA

DAC

DATA

DAC

DATA

DAC

DATA

Load DAC B input and DAC registers with new data.

Contents of DAC A, C, and D input registers are transferred

to the respective DAC registers. All outputs are updated.

0010

DAC

DATA

DAC

DATA

DAC

DATA

DAC

DATA

Load DAC C input and DAC registers with new data.

Contents of DAC A, B, and D input registers are transferred

to the respective DAC registers. All outputs are updated.

0011

DAC

DATA

DAC

DATA

DAC

DATA

DAC

DATA

Load DAC D input and DAC registers with new data.

Contents of DAC A, B, and C input registers are transferred

to the respective DAC registers. All outputs are updated

simultaneously.

0100

DAC

DATA

DAC

DATA

DAC

DATA

DAC

DATA

Load DAC A input register with new data. DAC outputs

remain unchanged.

0101

DAC

DATA

DAC

DATA

DAC

DATA

DAC

DATA

Load DAC B input register with new data. DAC outputs

remain unchanged.

0110

DAC

DATA

DAC

DATA

DAC

DATA

DAC

DATA

Load DAC C input register with new data. DAC outputs

remain unchanged.

0111

DAC

DATA

DAC

DATA

DAC

DATA

DAC

DATA

Load DAC D input register with new data. DAC outputs

remain unchanged.

1000

DAC

DATA

DAC

DATA

DAC

DATA

DAC

DATA

Data in all input registers is transferred to respective DAC

registers. All DAC outputs are updated simultaneously. New

data is loaded into DAC A input register.

1001

DAC

DATA

DAC

DATA

DAC

DATA

DAC

DATA

Data in all input registers is transferred to respective DAC

registers. All DAC outputs are updated simultaneously. New

data is loaded into DAC B input register.

1010

DAC

DATA

DAC

DATA

DAC

DATA

DAC

DATA

Data in all input registers is transferred to respective DAC

registers. All DAC outputs are updated simultaneously. New

data is loaded into DAC C input register.

1011

DAC

DATA

DAC

DATA

DAC

DATA

DAC

DATA

Data in all input registers is transferred to respective DAC

registers. All DAC outputs are updated simultaneously. New

data is loaded into DAC D input register.

1100

DAC

DATA

DAC

DATA

DAC

DATA

DAC

DATA

Load all DACs with new data and update all DAC outputs

simultaneously. Both input and DAC registers are updated

with new data.

1101

DAC

DATA

DAC

DATA

DAC

DATA

DAC

DATA

Load all input registers with new data. DAC outputs remain

unchanged.

Table 3. Command Byte Definitions

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15

MAX5842LEUB+

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Description:

Digital to Analog Converters - DAC 12-Bit 4Ch Precision DAC

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MAX5842LEUB+

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