MAX5842LEUB+ Datasheet MAX5842LEUB+, MAX5842MEUB+, MAX5842MEUB+T | P7-P9

MAX5842

Quad, 12-Bit, Low-Power, 2-Wire, Serial

Voltage-Output DAC

_______________________________________________________________________________________ 7

SETTLING TIME

(NEGATIVE)

MAX5842 toc22

2µs/div

OUT_

500mV/div

LOAD

= 200pF

CODE = C00 hex TO 400 hex

DIGITAL FEEDTHROUGH

MAX5842 toc23

40µs/div

OUT_

2mV/div

LOAD

= 200pF

SCL

= 12kHz

CODE = 000 hex

SCL

2V/div

CROSSTALK

MAX5842 toc24

4µs/div

OUTB

1mV/div

OUTA

2V/div

Typical Operating Characteristics (continued)

= +5V, R

= 5kΩ.)

Note 6: The ability to drive loads less than 5kΩ is not implied.

MAX5842

Quad, 12-Bit, Low-Power, 2-Wire, Serial

Voltage-Output DAC

8 _______________________________________________________________________________________

Detailed Description

The MAX5842 is a quad, 12-bit, voltage-output DAC

with an I

C/SMBus-compatible 2-wire interface. The

device consists of a serial interface, power-down cir-

cuitry, four input and DAC registers, four 12-bit resistor

string DACs, four unity-gain output buffers, and output

resistor networks. The serial interface decodes the

address and control bits, routing the data to the proper

input or DAC register. Data can be directly written to

the DAC register, immediately updating the device out-

put, or can be written to the input register without

changing the DAC output. Both registers retain data as

long as the device is powered.

DAC Operation

The MAX5842 uses a segmented resistor string DAC

architecture, which saves power in the overall system

and guarantees output monotonicity. The MAX5842’s

input coding is straight binary, with the output voltage

given by the following equation:

where N = 12 (bits), and D = the decimal value of the

input code (0 to 4095).

Output Buffer

The MAX5842 analog outputs are buffered by preci-

sion, unity-gain followers that slew 0.5V/µs. Each buffer

output swings rail-to-rail, and is capable of driving 5kΩ

in parallel with 200pF. The output settles to ±0.5LSB

within 4µs.

Power-On Reset

The MAX5842 features an internal POR circuit that ini-

tializes the device upon power-up. The DAC registers

are set to zero scale and the device is powered down,

with the output buffers disabled and the outputs pulled

to GND through the 100kΩ termination resistor.

Following power-up, a wake-up command must be initi-

ated before any conversions are performed.

Power-Down Modes

The MAX5842 has three software-controlled, low-

power, power-down modes. All three modes disable

the output buffers and disconnect the DAC resistor

strings from REF, reducing supply current draw to 1µA

and the reference current draw to less than 1µA. In

power-down mode 0, the device output is high imped-

ance. In power-down mode 1, the device output is

internally pulled to GND by a 1kΩ termination resistor.

In power-down mode 2, the device output is internally

pulled to GND by a 100kΩ termination resistor. Table 1

shows the power-down mode command words.

Upon wake-up, the DAC output is restored to its previ-

ous value. Data is retained in the input and DAC regis-

ters during power-down mode.

Digital Interface

The MAX5842 features an I

C/SMBus-compatible

2-wire interface consisting of a serial data line (SDA)

and a serial clock line (SCL). The MAX5842 is SMBus

compatible within the range of V

= 2.7V to 3.6V. SDA

and SCL facilitate bidirectional communication between

the MAX5842 and the master at rates up to 400kHz.

Figure 1 shows the 2-wire interface timing diagram. The

MAX5842 is a transmit/receive slave-only device, rely-

ing upon a master to generate a clock signal. The mas-

ter (typically a microcontroller) initiates data transfer on

the bus and generates SCL to permit that transfer.

A master device communicates to the MAX5842 by

transmitting the proper address followed by command

and/or data words. Each transmit sequence is framed

OUT

REF

()

Pin Description

PIN NAME FUNCTION

1 ADD Address Select. A logic high sets the address LSB to 1; a logic low sets the address LSB to zero.

2 SCL Serial Clock Input

Power Supply

4 GND Ground

5 SDA Bidirectional Serial Data Interface

6 REF Reference Input

7 OUTA DAC A Output

8 OUTB DAC B Output

9 OUTC DAC C Output

10 OUTD DAC D Output

MAX5842

Quad, 12-Bit, Low-Power, 2-Wire, Serial

Voltage-Output DAC

_______________________________________________________________________________________ 9

by a START (S) or REPEATED START (S

) condition and

a STOP (P) condition. Each word transmitted over the

bus is 8 bits long and is always followed by an

acknowledge clock pulse.

The MAX5842 SDA and SCL drivers are open-drain

outputs, requiring a pullup resistor to generate a logic

high voltage (see Typical Operating Circuit). Series

resistors R

are optional. These series resistors protect

the input stages of the MAX5842 from high-voltage

spikes on the bus lines, and minimize crosstalk and

undershoot of the bus signals.

Bit Transfer

One data bit is transferred during each SCL clock

cycle. The data on SDA must remain stable during the

high period of the SCL clock pulse. Changes in SDA

while SCL is high are control signals (see START and

STOP Conditions). Both SDA and SCL idle high when

the I

C bus is not busy.

START and STOP Conditions

When the serial interface is inactive, SDA and SCL idle

high. A master device initiates communication by issu-

ing a START condition. A START condition is a high-to-

low transition on SDA with SCL high. A STOP condition

is a low-to-high transition on SDA, while SCL is high

(Figure 2). A START condition from the master signals

the beginning of a transmission to the MAX5842. The

master terminates transmission by issuing a not

acknowledge followed by a STOP condition (see

Acknowledge Bit (ACK)). The STOP condition frees the

bus. If a repeated START condition (Sr) is generated

instead of a STOP condition, the bus remains active.

When a STOP condition or incorrect address is detect-

ed, the MAX5842 internally disconnects SCL from the

serial interface until the next START condition, minimiz-

ing digital noise and feedthrough.

Early STOP Conditions

The MAX5842 recognizes a STOP condition at any

point during transmission except if a STOP condition

occurs in the same high pulse as a START condition

(Figure 3). This condition is not a legal I

C format; at

least one clock pulse must separate any START and

STOP conditions.

Repeated START Conditions

A REPEATED START (S

) condition may indicate a

change of data direction on the bus. Such a change

occurs when a command word is required to initiate a

read operation. S

may also be used when the bus

master is writing to several I

C devices and does not

want to relinquish control of the bus. The MAX5842 ser-

ial interface supports continuous write operations with

or without an S

condition separating them. Continuous

POWER-DOWN

COMMAND BITS

PD1 PD0

MODE/FUNCTION

Power-up device. DAC output

restored to previous value.

Power-down mode 0. Power down

device with output floating.

Power-down mode 1. Power down

device with output terminated with

1kΩ to GND.

Power-down mode 2. Power down

device with output terminated with

100kΩ to GND.

Table 1. Power-Down Command Bits

SCL

SDA

STOP

CONDITION

START

CONDITION

REPEATED START CONDITIONSTART CONDITION

LOW

SU, DAT

SU, STA

BUF

HD, STA

SU, STO

HD, STA

HIGH

HD, DAT

Figure 1. 2-Wire Serial Interface Timing Diagram

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15

MAX5842LEUB+

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Maxim Integrated

Description:

Digital to Analog Converters - DAC 12-Bit 4Ch Precision DAC

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