LTC3812-5
28
38125fc
(max) plus any ringing, choose an 60V MOSFET. The
Si7850DP has:
BV
DSS
= 60V
R
DS(ON)
= 25mΩ (max)/31mΩ (nom),
δ= 0.007/°C,
C
MILLER
= (8.3nC – 2.8nC)/30V = 183pF,
V
GS(MILLER)
= 3.8V,
θ
JA
= 22°C/W.
This yields a nominal sense voltage of:
V
SNS(NOM)
= 6A • 1.3 • 0.025Ω = 195mV
To guarantee proper current limit at worst-case conditions,
increase nominal V
SNS
by at least 50% to 320mV (by tying
V
RNG
to 2V). To check if the current limit is acceptable at
V
SNS
= 320mV, assume a junction temperature of about
55°C above a 70°C ambient (ρ
125°C
= 1.7):
I
LIMIT
320mV
1.7 • 0.031
+
1
2
• 2.4A = 7.3A
and double-check the assumed T
J
in the MOSFET:
P
BOT
=
60V 5V
60V
• 7.3A
2
• 1.7 • 0.031 = 2.6W
T
J
= 70°C + 2.6W • 22°C/W = 127°C
Verify that the Si7850DP is also a good choice for the top
MOSFET by checking its power dissipation at current limit
and maximum input voltage, assuming a junction tempera-
ture of 30°C above a 70°C ambient (ρ
100°C
= 1.5):
P
MAIN
=
5V
60V
• 7.3A
2
1.5 • 0.031
()
+ 60V
2
•
7.3A
2
•2 •183pF •
1
5V 3.8V
+
1
3.8V
• 250kHz
= 0.206W + 1.32W = 1.53W
T
J
= 70°C + 1.53W • 22°C/W = 104°C
The junction temperature will be signifi cantly less at
nominal current, but this analysis shows that careful at-
tention to heat sinking on the board will be necessary in
this circuit.
Since V
OUT
> 4.7V, the INTV
CC
voltage can be generated
from V
OUT
with the internal LDO by connecting V
OUT
to
the EXTV
CC
pin. A small SOT23 MOSFET such as the
ZXMN10A07F can be used for the pass device if fault
timeout is enabled. Choose R
NDRV
to guarantee that fault
timeout is enabled when power dissipation of M3 exceeds
0.4W (max for 70°C ambient):
I
CC
= 250kHz • 2 • 18nC + 3mA = 12mA
R
NDRV
0.4W / 0.012A – 3V
270µA
= 112k
So, choose R
NDRV
= 100k.
C
IN
is chosen for an RMS current rating of about 3A at
85°C. The output capacitors are chosen for a low ESR
of 0.018Ω to minimize output voltage changes due to
inductor ripple current and load steps. The ripple voltage
will be only:
∆V
OUT(RIPPLE)
= ∆I
L(MAX)
• ESR = 2.4A • 0.018Ω
= 43mV
However, a 0A to 6A load step will cause an output change
of up to:
∆V
OUT(STEP)
= ∆I
LOAD
• ESR = 6A • 0.018Ω
= 108mV
An optional 10μF ceramic output capacitor is included
to minimize the effect of ESL in the output ripple. The
complete circuit is shown in Figure 15.
PC Board Layout Checklist
When laying out a PC board follow one of two suggested
approaches. The simple PC board layout requires a
dedicated ground plane layer. Also, for higher currents,
it is recommended to use a multilayer board to help with
heat sinking power components.
• The ground plane layer should not have any traces and
it should be as close as possible to the layer with power
MOSFETs.
• Place C
IN
, C
OUT
, MOSFETs, D1 and inductor all in one
compact area. It may help to have some components
on the bottom side of the board.
•
Use an immediate via to connect the components to
ground plane including SGND and PGND of LTC3812-5.
Use several bigger vias for power components.
APPLICATIONS INFORMATION
