18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFO
TM
262,144 x 9, 524,288 x 9
Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode)
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the rising edge
of WCLK and the rising edge of RCLK is less than tSKEW1, then EF deassertion may be delayed one extra RCLK cycle.
2. LD = HIGH.
3. First word latency: tSKEW1 + 1*TRCLK + tREF.
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go high (after one WCLK cycle pus tWFF). If the time between the rising
edge of the RCLK and the rising edge of the WCLK is less than tSKEW1, then the FF deassertion may be delayed one extra WCLK cycle.
2. LD = HIGH, OE = LOW, EF = HIGH
Figure 7. Write Cycle and Full Flag Timing (IDT Standard Mode)
D
0
- D
n
WEN
RCLK
REN
t
ENH
t
ENH
Q
0
- Q
n
DATA READ NEXT DATA READDATA IN OUTPUT REGISTER
t
SKEW1
(1)
4669 drw 10
WCLK
NO WRITE
1
2
1
2
t
DS
NO WRITE
t
WFF
t
WFF
t
WFF
t
A
t
ENS
t
ENS
t
SKEW1
(1)
t
DS
t
A
D
X
t
DH
t
CLK
t
CLKH
t
CLKL
D
X
+1
t
WFF
t
DH
NO OPERATION
RCLK
REN
4669 drw 11
EF
tCLK
tCLKH
tCLKL
tENH
tREF
tA
tOLZ
tOE
Q0 - Qn
OE
WCLK
(1)
tSKEW1
WEN
D0 - Dn
tENS
tENS
tENH
tDS
tDHS
D0
1
2
t
OLZ
NO OPERATION
LAST WORD
D0
D1
D1
tENS
tENH
tDS tDH
tOHZ
LAST WORD
t
REF
tENH
tENS
tA
tA
tREF
tENS
tENH
