PCA9633_5 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 05 — 25 July 2008 19 of 43
NXP Semiconductors
PCA9633
4-bit Fm+ I
2
C-bus LED driver
[1] OE applies to 16-pin version only. When OE = 1, LED output state is controlled only by OUTNE[1:0] bits (MODE2 register).
[2] External pull-up or LED current limiting resistor connects LEDn to V
DD
.
Table 18. Output transistors based on LEDOUT registers, INVRT and OUTDRV bits when OE = 0
[1]
LEDOUT INVRT OUTDRV Upper transistor
(V
DD
to LEDn)
Lower transistor
(LEDn to V
SS
)
LEDn state
00
LED driver off
0 0 off off high-Z
[2]
0 1 on off V
DD
1 0 off on V
SS
1 1 off on V
SS
01
LED driver on
0 0 off on V
SS
0 1 off on V
SS
1 0 off off high-Z
[2]
1 1 on off V
DD
10
Individual
brightness
control
0 0 off Individual PWM
(non-inverted)
V
SS
or high-Z
[2]
= PWMx value
0 1 Individual PWM
(non-inverted)
Individual PWM
(non-inverted)
V
SS
or V
DD
= PWMx value
1 0 off Individual PWM
(inverted)
high-Z
[2]
or V
SS
= 1 PWMx value
1 1 Individual PWM
(inverted)
Individual PWM
(inverted)
V
DD
or V
SS
= 1 PWMx value
11
Individual +
Group
dimming/blinking
0 0 off Individual + Group
PWM
(non-inverted)
V
SS
or high-Z
[2]
= PWMx/GRPPWM values
0 1 Individual PWM
(non-inverted)
Individual PWM
(non-inverted)
V
SS
or V
DD
= PWMx/GRPPWM values
1 0 off Individual + Group
PWM (inverted)
high-Z
[2]
or V
SS
= (1 PWMx) or
(1 GRPPWM) values
1 1 Individual PWM
(inverted)
Individual PWM
(inverted)
V
DD
or V
SS
=(1 PWMx) or
(1 GRPPWM) values
PCA9633_5 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 05 — 25 July 2008 20 of 43
NXP Semiconductors
PCA9633
4-bit Fm+ I
2
C-bus LED driver
7.8 Individual brightness control with group dimming/blinking
A 97 kHz fixed frequency signal with programmable duty cycle (8 bits, 256 steps) is used
to control individually the brightness for each LED.
On top of this signal, one of the following signals can be superimposed (this signal can be
applied to the 4 LED outputs):
A lower 190 Hz fixed frequency signal with programmable duty cycle (8 bits,
256 steps) is used to provide a global brightness control.
A programmable frequency signal from 24 Hz to
1
10.73
Hz (8 bits, 256 steps) with
programmable duty cycle (8 bits, 256 steps) is used to provide a global blinking
control.
Minimum pulse width for LEDn Brightness Control is 40 ns.
Minimum pulse width for Group Dimming is 20.48 µs.
When M = 1 (GRPPWM register value), the resulting LEDn Brightness Control + Group Dimming signal will have 2 pulses of
the LED Brightness Control signal (pulse width = N × 40 ns, with ‘N’ defined in PWMx register).
This resulting Brightness + Group Dimming signal above shows a resulting Control signal with M = 4 (8 pulses).
Fig 11. Brightness + Group Dimming signals
123456789101112 507
508
509
510
511
512
1234567891011
Brightness Control signal (LEDn)
M × 256 × 2 × 40 ns
with M = (0 to 255)
(GRPPWM Register)
N × 40 ns
with N = (0 to 255)
(PWMx Register)
256 × 40 ns = 10.24 µs
(97.6 kHz)
1234567812345678
Group Dimming signal
resulting Brightness + Group Dimming signal
256 × 2 × 256 × 40 ns = 5.24 ms (190.7 Hz)
002aab417
PCA9633_5 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 05 — 25 July 2008 21 of 43
NXP Semiconductors
PCA9633
4-bit Fm+ I
2
C-bus LED driver
8. Characteristics of the I
2
C-bus
The I
2
C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
8.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 12).
8.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 13).
8.2 System configuration
A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 14).
Fig 12. Bit transfer
mba607
data line
stable;
data valid
change
of data
allowed
SDA
SCL
Fig 13. Definition of START and STOP conditions
mba608
SDA
SCL
P
STOP condition
SDA
SCL
S
START condition

PCA9633DP1,118

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
LED Lighting Drivers LED DRVR 4BIT I2C
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union