VERSACLOCK
®
LOW-POWER CLOCK GENERATOR 10 REVISION P 04/01/16
5P49EE802 DATASHEET
External I
2
C Interface Condition
EEPROM Interface
The 5P49EE802 can store its configuration in an internal
EEPROM. The contents of the device's internal programming
registers can be saved to the EEPROM by issuing a save
instruction (ProgSave) and can be loaded back to the internal
programming registers by issuing a restore instruction
(ProgRestore).
To initiate a save or restore using I
2
C, only two bytes are
transferred. The Device Address is issued with the read/write
bit set to “0”, followed by the appropriate command code. The
save or restore instruction executes after the STOP condition
is issued by the Master, during which time the 5P49EE802 will
not generate Acknowledge bits. The 5P49EE802 will
acknowledge the instructions after it has completed execution
of them. During that time, the I
2
C bus should be interpreted as
busy by all other users of the bus.
On power-up of the 5P49EE802, an automatic restore is
performed to load the EEPROM contents into the internal
programming registers. The 5P49EE802 will be ready to
accept a programming instruction once it acknowledges its
7-bit I
2
C address.
Progwrite
Progwrite Command Frame
Writes can continue as long as a Stop condition is not sent and each byte will increment the register address.
