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5P49EE802NDGI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
REVISION P 04/01/16 25 VERSACLOCK
®
LOW-POWER CLOCK GENERATOR
5P49EE802 DATASHEET
Marking Diagram (NL28)
Notes:
1. “#” is the lot number.
2. YYWW is the last two digits of the year and week that the part was assembled.
3. “$” is the assembly mark code.
4. “I” indicates industrial temperature range.
Thermal Characteristics 28-pin VFQFPN
Landing Pattern
4802DI
#YYWW$
Parameter Symbol Conditions Min. Typ. Max. Units
Thermal Resistance Junction to Ambient
JA
Still air 48.6 C/W
JA
1 m/s air flow 41.7 C/W
JA
2.5 m/s air flow 37.7 C/W
Thermal Resistance Junction to Case
JC
55.1 C/W
X
D2
Y
AD
ZD
E2 AE ZE
GD
GE
X
D2
Y
AD
ZD
E2 AE ZE
GD
GE
0.25X(max)
0.76Yref
2.9G(min)
2.65A(max)
2.7E2/D2(max)
4.41Z(max)
Dimensions
0.25X(max)
0.76Yref
2.9G(min)
2.65A(max)
2.7E2/D2(max)
4.41Z(max)
Dimensions
Unit : mm
VERSACLOCK
®
LOW-POWER CLOCK GENERATOR 26 REVISION P 04/01/16
5P49EE802 DATASHEET
Package Outline and Package Dimensions (28-pin 4mm x 4mm QFN)
Package dimensions are kept current with JEDEC Publication No. 95
Ordering Information
“G” after the two-letter package code are the Pb-Free configuration and are RoHS compliant.
Millimeters
Symbol Min Max
A 0.80 1.00
A1 0 0.05
A3 0.20 Reference
b 0.15 0.25
e 0.40 BASIC
N28
N
D
7
N
E
7
D x E BASIC 4.00 x 4.00
D2 2.50 2.70
E2 2.50 2.70
L 0.30 0.50
Part / Order Number Marking Shipping Packaging Package Temperature
5P49EE802NDGI See page 26 Tray 28-pin VFQFPN -40° to +85°C
5P49EE802NDGI8 Tape and Reel 28-pin VFQFPN -40° to +85°C
Sawn
Singulation
1
2
N
E
D
Index Area
Top View
Seating Plane
A3
A1
C
A
L
E2
E2
2
D2
D2
2
e
C0.08
(Ref)
N
D
& N
E
Odd
(Ref)
N
D
& N
E
Even
(N
D
-1)x
(Ref)
e
N
1
2
b
Thermal Base
EP – Exposed thermal pad
should be externally
connected to ground.
(Typ)
If N
D
& N
E
are Even
(N
E
-1)x
(Ref)
e
e
2
REVISION P 04/01/16 27 VERSACLOCK
®
LOW-POWER CLOCK GENERATOR
5P49EE802 DATASHEET
Revision History
Rev. Date Originator Description of Change
-- 10/14/09 R.Willner Initial Preliminary Datasheet
A 11/20/09 R.Willner No_PD bit inclusion - 32kHz clock on/off in Config 00.
B 3/25/10 R.Willner Typographical changes. Correct spread spectrum calculations.
C 6/02/10 R.Willner Typographical changes. Default configuration.
D 9/08/10 R.Willner Updated thermal pad and dimensions on package drawing. Input Clock max voltage
swing 1.8V. Power ramp sequence.
E 10/29/10 R. Willner Typographical changes. Loop filter calculations. Default register bit corrections.
F 01/19/11 R. Willner Corrected notes for top-side marking.
G 04/13/11 R. Willner 1. Updated SCLK and SDA pin descriptions
2. Updated DC Electrical Char table for 1.8V LVTTL; added VIH and VIL.
3. Updated “Lock Time/PLL Lock Time from shutdown mode” Typ. and Max. specs in AC
Timing Electrical Char table.
H 05/04/11 R. Willner Added Landing Pattern diagram.
J 08/24/11 R. Willner Corrected SRC1 connections in block diagram.
K 0930/11 R. Willner Updated Power-up/Power-down Sequence notes.
L 10/17/11 R. Willner 1. Added VDDOx specs to Recomended Operations table
2. Updated Power-up/down Sequence diagrams
M 07/25/12 R. Willner 1. Added pin 1 indicator dot on marking diagram.
2. Corrected typo in Register Map table; SLEWx[0:1] was changed to SLEWx[1:0]
N 09/10/15 A. Borodulin 1. Corrected minor textual typos throughout.
2. Update VOH/VOL and VIH/VIL values in 1.8V LVTTL DC table.
3. Update t4 and t5 specs in AC Electrical Characteristics table; added specific 3.3V to
title.
4. Created separate 2.5V and 1.8V Ac Electrical Characteristics tables.
5. Added footnotes to Spread Spectrum Generation table.
P 04/01/16 Z. Bhinder 1. Updated Default register Hex values throughout entire Programming Registers table.
2. Updated note 2 under Pin Descriptions.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28

5P49EE802NDGI

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Manufacturer:
IDT
Description:
Clock Generators & Support Products VERSACLOCK LOW POWER PLL
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