OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

AD8114ASTZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
Data Sheet AD8114/AD8115
Rev. C | Page 19 of 25
One important consideration in using parallel programming is
that the
RESET
signal does not reset all registers in the AD8114/
AD8115. When taken low, the
RESET
signal only sets each output
to the disabled state. This is helpful during power-up to ensure
that two parallel outputs are not active at the same time.
After initial power-up, the internal registers in the device generally
have random data, even though the
RESET
signal was asserted.
If parallel programming is used to program one output, then
that output is properly programmed, but the rest of the device
has a random program state depending on the internal register
content at power-up. Therefore, when using parallel programming,
it is essential that all outputs be programmed to a desired state
after power-up. This ensures that the programming matrix is
always in a known state. From then on, parallel programming
can be used to modify a single output or more at a time.
In similar fashion, if both
CE
and
UPDATE
are taken low after
initial power-up, the random power-up data in the shift register
is programmed into the matrix. Therefore, to prevent the
crosspoint from being programmed into an unknown state, do
not apply low logic levels to both
CE
and
UPDATE
after power
is initially applied. Programming the full shift register one time
to a desired state by either serial or parallel programming after
initial power-up eliminates the possibility of programming the
matrix to an unknown state.
To change the programming of an output via parallel
programming,
SER
/PAR and
UPDATE
should be taken high
and
CE
should be taken low. The CLK signal should be in the
high state. The 4-bit address of the output to be programmed
should be put on A0 to A3. The first four data bits (D0 to D3)
should contain the information that identifies the input that
gets programmed to the output that is addressed. The fourth
data bit (D4) determines the enabled state of the output. If D4 is
low (output disabled), then the data on D0 to D3 does not matter.
After the desired address and data signals have been established,
they can be latched into the shift register by a high to low transition
of the CLK signal. The matrix is not programmed, however, until
the
UPDATE
signal is taken low. It is thus possible to latch in
new data for several or all of the outputs first via successive
negative transitions of CLK while
UPDATE
is held high, and
then have all the new data take effect when UPDATE goes low.
This technique should be used when programming the device
for the first time after power-up when using parallel programming.
POWER-ON RESET
When powering up the AD8114/AD8115, it is usually desirable
to have the outputs come up in the disabled state. When taken
low, the
RESET
pin causes all outputs to be in the disabled state.
However, the
RESET
signal does not reset all registers in the
AD8114/AD8115. This is important when operating in the
parallel programming mode.
Please refer to that section for information about programming
internal registers after power-up. Serial programming programs
the entire matrix each time, so no special considerations apply.
Since the data in the shift register is random after power-up, it
should not be used to program the matrix, or the matrix can
enter unknown states. To prevent this, do not apply logic low
signals to both
CE
and
UPDATE
initially after power-up. The
shift register should first be loaded with the desired data, and
then
UPDATE
can be taken low to program the device.
The
RESET
pin has a 20 kΩ pull-up resistor to DVDD that can
be used to create a simple power-up reset circuit. A capacitor
from
RESET
to ground holds
RESET
low for some time while
the rest of the device stabilizes. The low condition causes all the
outputs to be disabled. The capacitor then charges through the
pull-up resistor to the high state, thus allowing full programming
capability of the device.
GAIN SELECTION
The 16 × 16 crosspoints come in two versions, depending on
the gain of the analog circuit paths that is desired. The AD8114
device is unity gain and can be used for analog logic switching
and other applications where unity gain is desired. The AD8114
can also be used for the input and interior sections of larger
crosspoint arrays where termination of output signals is not
usually used. The AD8114 outputs have very high impedance
when their outputs are disabled.
The AD8115 can be used for devices that are used to drive a
terminated cable with its outputs. This device has a built-in gain
of 2 that eliminates the need for a gain-of-2 buffer to drive a
video line. Its high output disabled impedance minimizes
signal degradation when paralleling additional outputs.
CREATING LARGER CROSSPOINT ARRAYS
The AD8114/AD8115 are high density building blocks for
creating crosspoint arrays of dimensions larger than 16 × 16.
Various features, such as output disable, chip enable, and gain-
of-1 and gain-of-2 options, are useful for creating larger arrays.
When required for customizing a crosspoint array size, they can
be used with the AD8108 and AD8109, a pair of (unity gain and
gain-of-2) 8 × 8 video crosspoint switches, or with the AD8110
and AD8111, a pair of (unity gain and gain-of-2) 16 × 8 video
crosspoint switches.
The first consideration in constructing a larger crosspoint is to
determine the minimum number of devices required. The 16 ×
16 architecture of the AD8114/AD8115 contains 256 points, which
is a factor of 64 greater than a 4 × 1 crosspoint (or multiplexer).
The printed circuit board area, power consumption, and design
effort savings are readily apparent when compared to using
these smaller devices.
AD8114/AD8115 Data Sheet
Rev. C | Page 20 of 25
For a nonblocking crosspoint, the number of points required is
the product of the number of inputs multiplied by the number
of outputs. Nonblocking requires that the programming of a given
input to one or more outputs does not restrict the availability of
that input to be a source for any other outputs.
Some nonblocking crosspoint architectures require more than
this minimum as calculated above. Also, there are blocking
architectures that can be constructed with fewer devices than
this minimum. These systems have connectivity available on a
statistical basis that is determined when designing the overall
system.
The basic concept in constructing larger crosspoint arrays is to
connect inputs in parallel in a horizontal direction and to wire-
OR the outputs together in the vertical direction. The meaning
of horizontal and vertical can best be understood by looking at
a diagram. Figure 48 illustrates this concept for a 32 × 32
crosspoint array that uses four AD8114 or AD8115 devices.
AD8114
OR
AD8115
AD8114
OR
AD8115
AD8114
OR
AD8115
AD8114
OR
AD8115
16
16
16
16
R
TERM
IN 00–
15
16
16
R
TERM
IN 16
–
31
16
16
16
16
01070-048
Figure 48. 32 × 32 Crosspoint Array Using Four AD8114 or AD8115 Devices
The inputs are each uniquely assigned to each of the 32 inputs
of the two devices and terminated appropriately. The outputs
are wired-OR’ed together in pairs. The output from only one of
a wire-O R’e d pair should be enabled at any given time. The device
programming software must be properly written to cause this to
happen.
16
R
TERM
IN 00–15
8
8
IN 16
–31
IN 32
–47
IN 48–63
IN 64–79
IN 80–
95
IN 96–111
IN 112
–127
8
8
8
8
RANK 2
32:16 NONBLOCKING
(32:32 BLOCKING)
RANK 1
(8 × AD8114)
128:32
16
R
TERM
8
8
16
R
TERM
8
8
16
R
TERM
8
8
16
R
TERM
8
8
16
R
TERM
8
8
16
R
TERM
8
8
16
R
TERM
8
8
AD8115
8
1kΩ
8
1kΩ
8
1kΩ
8
1k
Ω
AD8115
OUT 00
Ð15
NONBLOCKING
ADDITIONAL
16 OUTPUTS
(SUBJECT
TO BLOCKING)
AD8114
AD8114
AD8114
AD8114
AD8114
AD8114
AD8114
AD8114
01070-049
Figure 49. Nonblocking 128 × 16 Array (128 × 32 Blocking)
Data Sheet AD8114/AD8115
Rev. C | Page 21 of 25
Using additional crosspoint devices in the design can lower the
number of outputs that must be wire-OR’ed together. Figure 49
shows a block diagram of a system using eight AD8114 devices
and two AD8115 devices to create a nonblocking, gain-of-2,
128 × 16 crosspoint that restricts the wire-OR’ing at the
output to only four outputs.
Additionally, by using the lower eight outputs from each of the
two Rank 2 AD8115 devices, a blocking 128 × 32 crosspoint
array can be realized. There are, however, some drawbacks to
this technique. The offset voltages of the various cascaded
devices accumulates, and the bandwidth limitations of the
devices compound. In addition, the extra devices consume
more current and take up more board space. Once again, the
overall system design specifications determine how to make
the various tradeoffs.
MULTICHANNEL VIDEO
The excellent video specifications of the AD8114/AD8115 make
them ideal candidates for creating composite video crosspoint
switches. These can be made quite dense by taking advantage of
the high level of integration of the AD8114/AD8115 and the
fact that composite video requires only one crosspoint channel
per system video channel. There are, however, other video
formats that can be routed with the AD8114/AD8115 requiring
more than one crosspoint channel per video channel.
Some systems use twisted-pair wiring to carry video signals. These
systems utilize differential signals and can lower costs because
they use lower cost cables, connectors and termination methods.
They also have the ability to lower crosstalk and reject common-
mode signals, which can be important for equipment that
operates in noisy environments or where common-mode voltages
are present between transmitting and receiving equipment.
In such systems, the video signals are differential; there is a
positive and negative (or inverted) version of the signals. These
complementary signals are transmitted onto each of the two
wires of the twisted pair, yielding a first-order zero common-
mode voltage. At the receive end, the signals are differentially
received and converted back into a single-ended signal.
When switching these differential signals, two channels are
required in the switching element to handle the two differential
signals that make up the video channel. Thus, one differential
video channel is assigned to a pair of crosspoint channels, both
input and output. For a single AD8114/AD8115, eight differential
video channels can be assigned to the 16 inputs and 16 outputs.
This effectively forms an 8 × 8 differential crosspoint switch.
Programming such a device requires that inputs and outputs be
programmed in pairs. This information can be deduced by
inspection of the programming format of the AD8114/AD8115
and the requirements of the system.
There are other analog video formats requiring more than one
analog circuit per video channel. One 2-circuit format that is
commonly being used in systems such as satellite TV, digital
cable boxes, and higher quality VCRs is called S-video or Y/C
video. This format carries the brightness (luminance or Y)
portion of the video signal on one channel and the color
(chrominance, chroma, or C) on a second channel.
Since S-video also uses two separate circuits for one video
channel, creating a crosspoint system requires assigning one
video channel to two crosspoint channels, as in the case of a
differential video system. Aside from the nature of the video
format, other aspects of these two systems are the same.
There are yet other video formats using three channels to carry
the video information. Video cameras produce RGB (red, green,
blue) directly from the image sensors. RGB is also the usual
format used by computers internally for graphics. RGB can be
converted to Y, R-Y, B-Y format, sometimes called YUV format.
These 3-circuit video standards are referred to as component
analog video.
The component video standards require three crosspoint channels
per video channel to handle the switching function. In a fashion
similar to the 2-circuit video formats, the inputs and outputs
are assigned in groups of three, and the appropriate logic
programming is performed to route the video signals.
CROSSTALK
Many systems, such as broadcast video, that handle numerous
analog signal channels have strict requirements for keeping the
various signals from influencing any of the others in the system.
Crosstalk is the term used to describe the coupling of the
signals of other nearby channels to a given channel.
When there are many signals in close proximity in a system, as
is undoubtedly the case in a system that uses the AD8114/
AD8115, the crosstalk issues can be quite complex. A good
understanding of the nature of crosstalk and some definition
of terms is required to specify a system that uses one or more
AD8114/AD8115 devices.
Types of Crosstalk
Crosstalk can be propagated by means of any of three methods.
These fall into the categories of electric field, magnetic field,
and sharing of common impedances. This section explains
these effects.
Every conductor can be both a radiator of electric fields and a
receiver of electric fields. The electric field crosstalk mechanism
occurs when the electric field created by the transmitter propagates
across a stray capacitance (for example, free space) and couples
with the receiver and induces a voltage. This voltage is an
unwanted crosstalk signal in any channel that receives it.
Currents flowing in conductors create magnetic fields that circulate
around the currents. These magnetic fields then generate voltages
in any other conductors whose paths they link. The undesired
induced voltages in these other channels are crosstalk signals.
The channels that crosstalk can be said to have a mutual
inductance that couples signals from one channel to another.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

AD8114ASTZ

Mfr. #:
Buy AD8114ASTZ
Manufacturer:
Analog Devices Inc.
Description:
Analog & Digital Crosspoint ICs 225MHz 16 x 16
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet