AD8114ASTZ Datasheet AD8115ASTZ, AD8114ASTZ | P7-P9

Data Sheet AD8114/AD8115

Rev. C | Page 7 of 25

Table 6. Operation Truth Table

UPDATE

CLK DATA IN DATA OUT

RESET

SER

/ PAR

Operation/Comment

1 X X X X X X No change in logic.

0 1 f Data

Data

i-80

1 0 The data on the serial DATA IN line is loaded into serial register.

The first bit clocked into the serial register appears at DATA

OUT 80 clocks later.

0 1 f D0…D4,

A0… A3

Not applicable in

parallel mode

1 1 The data on the parallel data lines, D0 to D4, are loaded into

the 80 bit serial shift register location addressed by A0 to A3.

0 0 X X X 1 X Data in the 80-bit shift register transfers into the parallel

latches that control the switch array. Latches are transparent.

X X X X X 0 X Asynchronous operation. All outputs are disabled. Remainder

of logic is unchanged.

CLK

4 TO 16 DECODER

CLK

256

DATA IN

(SERIAL)

(OUTPUT

ENABLE)

SER/PAR

UPDATE

OUT0 EN

DATA

OUT

PARALLEL

DATA

CLK

OUT1 EN

OUT2 EN

OUT3 EN

OUT4 EN

OUT5 EN

OUT6 EN

OUT7 EN

QCLR

OUT15

OUTPUT ENABLE

SWITCH MATRIX

CLK

DECODE

QCLR

OUT0

OUT1

QCLR

OUT14

OUT15

CLK

OUT15

OUT8 EN

OUT9 EN

OUT10 EN

OUT11 EN

OUT12 EN

OUT13 EN

OUT14 EN

OUT15 EN

OUTPUT

ADDRESS

RESET

(OUTPUT ENABLE)

01070-011

Figure 4. Logic Diagram

AD8114/AD8115 Data Sheet

Rev. C | Page 8 of 25

ABSOLUTE MAXIMUM RATINGS

Table 7.

Parameter Rating

Supply Voltage 12.0 V

Internal Power Dissipation

AD8114/AD8115 100-Lead

Plastic LQFP (ST)

2.6 W

Input Voltage ±V

Output Short-Circuit Duration Observe power derating curves

Storage Temperature Range

−65°C to +125°C

Specification is for device in free air (T

= 25°C). 100-lead plastic LQFP (ST):

= 40°C/W.

Maximum reflow temperatures are to JEDEC industry standard J-STD-020.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

MAXIMUM POWER DISSIPATION

The maximum power that can be safely dissipated by the

AD8114/AD8115 is limited by the associated rise in junction

temperature. The maximum safe junction temperature for

plastic encapsulated devices is determined by the glass transition

temperature of the plastic, approximately 125°C. Temporar ily

exceeding this limit may cause a shift in parametric performance

due to a change in the stresses exerted on the die by the package.

Exceeding a junction temperature of 125°C for an extended

period can result in device failure.

While the AD8114/AD8115 are internally short-circuit protected,

this may not be sufficient to guarantee that the maximum junction

temperature (125°C) is not exceeded under all conditions. To

ensure proper operation, it is necessary to observe the maximum

power derating curves shown in Figure 5.

= 125

AMBIENT TEMPERATURE (

MAXIMUM POWER DISSIPATION (Ω)

–

50 –

40 –

–20

–10

40 50

80 90

01070-004

Figure 5. Maximum Power Dissipation vs. Temperature

ESD CAUTION

Data Sheet AD8114/AD8115

Rev. C | Page 9 of 25

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

01070-005

NC = NO CONNECT

RESET

DATA OUT

CLK

DATA IN

UPDATE

SER/PAR

AVCC13/14

OUT13

AVEE12/13

OUT12

AVCC11/12

OUT11

AVEE10/11

OUT10

AVCC09/10

OUT09

AVEE08/09

OUT08

AVCC07/08

OUT07

DGND

AGND

IN08

AGND

IN09

AGND

DVCC

IN10

AGND

IN11

IN12

AGND

IN13

AGND

IN14

AGND

IN15

AGND

AVEE

AVCC

AVCC15

OUT15

AVEE14/15

OUT14

AGND

DGND

DVCC

AGND

IN07

AGND

IN06

AGND

IN05

AGND

IN04

IN03

AGND

IN02

AGND

IN01

AGND

IN00

AGND

AVEE

AVCC

AVCC00

OUT00

AVEE00/01

OUT01

AGND

AVEE06/07

OUT06

AVCC05/06

OUT05

AVEE04/05

OUT04

AVCC03/04

OUT03

AVEE02/03

OUT02

AVCC01/02

100

PIN 1

AD8114/AD8115

TOP VIEW

(Not to Scale)

Figure 6. Pin Configuration

Table 8. Pin Function Descriptions

Pin No. Mnemonic Description

58, 60, 62, 64, 66, 68, 70, 72,

4, 6, 8, 10, 12, 14, 16, 18

INxx Analog Inputs. xx = Channel 00 through Channel 15.

DATA IN

Serial Data Input, TTL Compatible.

CLK

Clock, TTL Compatible. Falling edge triggered.

98 DATA OUT Serial Data Out, TTL Compatible.

UPDATE

Enable (Transparent) Low. Allows serial register to connect directly to switch matrix. Data

latched when high.

100

RESET

Disable Outputs, Active Low.

Chip Enable, Enable Low. Must be low to clock in and latch data.

SER

/PAR Selects Serial Data Mode, Low or Parallel Data Mode, High. Must be connected.

53, 51, 49, 47, 45, 43, 41, 39,

37, 35, 33, 31, 29, 27, 25, 23

OUTyy Analog Outputs. yy = Channel 00 through Channel 15.

3, 5, 7, 9, 11, 13, 15, 17, 19, 57,

59, 61, 63, 65, 67, 69, 71, 73

AGND Analog Ground for Inputs and Switch Matrix. Must be connected.

1, 75

DVCC

+5 V for Digital Circuitry.

2, 74 DGND Ground for Digital Circuitry.

20, 56 AVEE −5 V for Inputs and Switch Matrix.

21, 55 AVCC +5 V for Inputs and Switch Matrix.

54, 50, 46, 42, 38, 34, 30, 26, 22 AVCCxx/yy +5 V for Output Amplifier that is Shared by Channels xx and yy. Must be connected.

52, 48, 44, 40, 36, 32, 28, 24 AVEExx/yy −5 V for Output Amplifier that is Shared by Channels xx and yy. Must be connected.

84 A0 Parallel Data Input, TTL Compatible (output select LSB).

83 A1 Parallel Data Input, TTL Compatible (output select).

82 A2 Parallel Data Input, TTL Compatible (output select).

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P25

AD8114ASTZ

Mfr. #:

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Manufacturer:

Analog Devices Inc.

Description:

Analog & Digital Crosspoint ICs 225MHz 16 x 16

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AD8114ASTZ

AD8114ASTZ

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