AD8114/AD8115 Data Sheet
Rev. C | Page 18 of 25
THEORY OF OPERATION
The AD8114 (G = 1) and AD8115 (G = 2) are crosspoint arrays
with 16 outputs, each of which can be connected to any one of 16
inputs. Organized by output row, 16 switchable transconductance
stages are connected to each output buffer in the form of a 16-to-1
multiplexer. Each of the 16 rows of transconductance stages are
wired in parallel to the 16 input pins, for a total array of 256
transconductance stages. Decoding logic for each output selects
one (or none) of the transconductance stages to drive the output
stage. The transconductance stages are NPN-input differential
pairs, sourcing current into the folded cascode output stage.
The compensation network and emitter follower output buffer
are in the output stage. Voltage feedback sets the gain, with the
AD8114 configured as a unity gain follower, and the AD8115
configured as a gain-of-2 amplifier with a feedback network.
This architecture provides drive for a reverse-terminated video
load (150 Ω), with low differential gain and phase error for
relatively low power consumption. Power consumption is
further reduced by disabling outputs and transconductance
stages that are not in use. The user notices a small increase in
input bias current as each transconductance stage is enabled.
Features of the AD8114 and AD8115 simplify the construction
of larger switch matrices. The unused outputs of both devices
can be disabled to a high impedance state, allowing the outputs
of multiple ICs to be bused together. In the case of the AD8115,
a feedback isolation scheme is used so that the impedance of the
gain-of-2 feedback network does not load the output. Because
no additional input buffering is necessary, high input resistance
and low input capacitance are easily achieved without additional
signal degradation. To control enable glitches, it is recommended
that the disabled output voltage be maintained within its normal
enabled voltage range (±3.3 V). If necessary, the disabled output
can be kept from drifting out of range by applying an output
load resistor to ground.
A flexible TTL-compatible logic interface simplifies the
programming of the matrix. Both parallel and serial loading
into a first rank of latches programs each output. A global latch
simultaneously updates all outputs. A power-on reset pin is
available to avoid bus conflicts by disabling all outputs.
APPLICATIONS
The AD8114/AD8115 have two options for changing the
programming of the crosspoint matrix. In the first option a
serial word of 80 bits can be provided that updates the entire
matrix each time. The second option allows for changing the
programming of a single output via a parallel interface. The
serial option requires fewer signals, but more time (clock cycles)
for changing the programming, while the parallel programming
technique requires more signals, but can change a single output
at a time and requires fewer clock cycles to complete programming.
Serial Programming
The serial programming mode uses the
CE
, CLK, DATA IN,
UPDATE
, and
SER
/PAR device pins. The first step is to assert a
low on
SER
/PAR to enable the serial programming mode.
CE
for the chip must be low to allow data to be clocked into the
device. The
CE
signal can be used to address an individual
device when devices are connected in parallel.
The
UPDATE
signal should be high during the time that data is
shifted into the serial port of the device. Although the data still
shifts in when
UPDATE
is low, the transparent, asynchronous
latches allow the shifting data to reach the matrix. This causes
the matrix to try to update to every intermediate state as defined
by the shifting data.
The data at DATA IN is clocked in at every down edge of CLK.
A total of 80 bits must be shifted in to complete the programming.
For each of the 16 outputs, there are four bits (D0 to D3) that
determine the source of its input followed by one bit (D4) that
determines the enabled state of the output. If D4 is low (output
disabled), the four associated bits (D0 to D3) do not matter
because no input is switched to that output.
The most significant output address data is shifted in first, and
then following in sequence until the least significant output
address data is shifted in. At this point
UPDATE
can be taken
low, which causes the programming of the device according to
the data that was just shifted in. The
UPDATE
registers are
asynchronous, and when
UPDATE
is low (and
CE
is low),
they are transparent.
If more than one AD8114/AD8115 device is to be serially
programmed in a system, the DATA OUT signal from one
device can be connected to the DATA IN of the next device to
form a serial chain. All of the CLK,
CE
,
UPDATE
, and
SER
/PAR pins should be connected in parallel and operated as
described above. The serial data is input to the DATA IN pin of
the first device of the chain, and it ripples on through to the last.
Therefore, the data for the last device in the chain should come
at the beginning of the programming sequence. The length of
the programming sequence (80 bits) is multiplied by the
number of devices in the chain.
Parallel Programming
While using the parallel programming mode, it is not necessary
to reprogram the entire device when making changes to the matrix.
In fact, parallel programming allows the modification of a single
output at a time. Since this takes only one CLK/
UPDATE
cycle,
significant time savings can be realized by using parallel
programming.
