Data Sheet AD8114/AD8115
Rev. C | Page 9 of 25
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
01070-005
NC = NO CONNECT
RESET
CE
DATA OUT
CLK
DATA IN
UPDATE
SER/PAR
NC
NC
NC
NC
NC
NC
NC
NC
NC
A0
A1
A2
A3
D0
D1
D2
D3
D4
26
AVCC13/14
27
OUT13
28
AVEE12/13
29
OUT12
30
AVCC11/12
31
OUT11
32
AVEE10/11
33
OUT10
34
AVCC09/10
35
OUT09
36
AVEE08/09
37
OUT08
38
AVCC07/08
39
OUT07
2
DGND
3
AGND
4
IN08
7
AGND
6
IN09
5
AGND
1
DVCC
8
IN10
9
AGND
10
IN11
12
IN12
13
AGND
14
IN13
15
AGND
16
IN14
17
AGND
18
IN15
19
AGND
20
AVEE
21
AVCC
22
AVCC15
23
OUT15
24
AVEE14/15
25
OUT14
11
AGND
74
DGND
DVCC
73
AGND
72
IN07
69
AGND
70
IN06
71
AGND
75
68
IN05
67
AGND
66
IN04
64
IN03
63
AGND
62
IN02
61
AGND
60
IN01
59
AGND
58
IN00
57
AGND
56
AVEE
55
AVCC
54
AVCC00
53
OUT00
52
AVEE00/01
51
OUT01
65
AGND
40
AVEE06/07
41
OUT06
42
AVCC05/06
43
OUT05
44
AVEE04/05
45
OUT04
46
AVCC03/04
47
OUT03
48
AVEE02/03
49
OUT02
50
AVCC01/02
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PIN 1
AD8114/AD8115
TOP VIEW
(Not to Scale)
Figure 6. Pin Configuration
Table 8. Pin Function Descriptions
Pin No. Mnemonic Description
58, 60, 62, 64, 66, 68, 70, 72,
4, 6, 8, 10, 12, 14, 16, 18
INxx Analog Inputs. xx = Channel 00 through Channel 15.
Serial Data Input, TTL Compatible.
Clock, TTL Compatible. Falling edge triggered.
98 DATA OUT Serial Data Out, TTL Compatible.
95
UPDATE
Enable (Transparent) Low. Allows serial register to connect directly to switch matrix. Data
latched when high.
100
RESET
Disable Outputs, Active Low.
CE
Chip Enable, Enable Low. Must be low to clock in and latch data.
94
SER
/PAR Selects Serial Data Mode, Low or Parallel Data Mode, High. Must be connected.
53, 51, 49, 47, 45, 43, 41, 39,
37, 35, 33, 31, 29, 27, 25, 23
OUTyy Analog Outputs. yy = Channel 00 through Channel 15.
3, 5, 7, 9, 11, 13, 15, 17, 19, 57,
59, 61, 63, 65, 67, 69, 71, 73
AGND Analog Ground for Inputs and Switch Matrix. Must be connected.
+5 V for Digital Circuitry.
2, 74 DGND Ground for Digital Circuitry.
20, 56 AVEE −5 V for Inputs and Switch Matrix.
21, 55 AVCC +5 V for Inputs and Switch Matrix.
54, 50, 46, 42, 38, 34, 30, 26, 22 AVCCxx/yy +5 V for Output Amplifier that is Shared by Channels xx and yy. Must be connected.
52, 48, 44, 40, 36, 32, 28, 24 AVEExx/yy −5 V for Output Amplifier that is Shared by Channels xx and yy. Must be connected.
84 A0 Parallel Data Input, TTL Compatible (output select LSB).
83 A1 Parallel Data Input, TTL Compatible (output select).
82 A2 Parallel Data Input, TTL Compatible (output select).