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PCF8577CT/3,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33
PCF8577C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 10 October 2014 10 of 33
NXP Semiconductors
PCF8577C
LCD direct/duplex driver with I²C-bus interface
8.1.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is not limited. Each byte is followed by one acknowledge bit. The
acknowledge bit is a HIGH level put on the I
2
C-bus by the transmitter whereas the master
generates an extra acknowledge related clock pulse. A slave receiver which is addressed
must generate an acknowledge after the reception of each byte. Also a master must
generate an acknowledge after the reception of each byte that has been clocked out of
the slave transmitter. The device that acknowledges has to pull down the SDA line during
the acknowledge clock pulse, set-up and hold times must be taken into account. A master
receiver must signal an end of data to the transmitter by not generating an acknowledge
on the last byte that has been clocked out of the slave. In this event, the transmitter must
leave the data line HIGH to enable the master to generate a STOP condition.
8.2 Slave address
The PCF8577C slave address is shown in Table 7.
Before any data is transmitted on the I
2
C-bus, the device which should respond is
addressed first. The addressing is always done with the first byte transmitted after the
start procedure.
Fig 8. System configuration
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2
C-bus
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Table 7. I
2
C slave address byte
Slave address R/W
Bit 7
MSB
6 5 4 3 2 1 0
LSB
01110100
PCF8577C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 10 October 2014 11 of 33
NXP Semiconductors
PCF8577C
LCD direct/duplex driver with I²C-bus interface
8.3 I
2
C-bus protocol
The PCF8577C I
2
C-bus protocol is shown in Figure 10.
The PCF8577C is a slave receiver and has a fixed slave address (see Table 7
). All
PCF8577Cs with the same slave address acknowledge the slave address in parallel.
The second byte is always the control byte and is loaded into the control register of each
PCF8577C connected to the I
2
C-bus. All addressed devices acknowledge the control
byte. Subsequent data bytes are loaded into the segment registers of the selected device.
Any number of data bytes may be loaded in one transfer and in an expanded system
rollover of the SBV from 111 111 to 000 000 is allowed. If a STOP (P) condition is given
after the control byte acknowledge, the segment data remains unchanged. This allows the
BANK bit to be toggled without changing the segment register contents. During loading of
segment data, only the selected PCF8577C gives an acknowledge. Loading is terminated
by generating a STOP (P) condition.
9. Safety notes
Fig 10. I
2
C-bus protocol
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CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling
electrostatic sensitive devices.
Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or
equivalent standards.
CAUTION
Static voltages across the liquid crystal display can build up when the LCD supply voltage
(V
LCD
) is on while the IC supply voltage (V
DD
) is off, or vice versa. This may cause unwanted
display artifacts. To avoid such artifacts, V
LCD
and V
DD
must be applied or removed together.
CAUTION
Semiconductors are light sensitive. Exposure to light sources can cause the IC to
malfunction. The IC must be protected against light. The protection must be applied to all
sides of the IC.
PCF8577C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 10 October 2014 12 of 33
NXP Semiconductors
PCF8577C
LCD direct/duplex driver with I²C-bus interface
10. Limiting values
[1] Values with respect to V
DD
.
[2] Pass level; Human Body Model (HBM), according to Ref. 6 “
JESD22-A114”.
[3] Pass level; Machine Model (MM), according to Ref. 7 “
JESD22-A115”.
[4] Pass level; latch-up testing according to Ref. 8 “
JESD78” at maximum ambient temperature (T
amb(max)
).
[5] According to the store and transport requirements (see Ref. 12 “
UM10569”) the devices have to be stored at a temperature of +8 C to
+45 C and a humidity of 25 % to 75 %.
Table 8. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DD
supply voltage 0.5 +8.0 V
V
LCD
LCD supply voltage
[1]
V
DD
8.0 V
DD
V
V
I
input voltage 0.5 V
DD
+0.5 V
V
O
output voltage on each of the pins
S1 to S32 and BP1 and BP2
[1]
0.5 +8.0 V
I
I
input current 20 +20 mA
I
O
output current 25 +25 mA
I
DD
supply current 50 +50 mA
I
SS
ground supply current 50 +50 mA
I
DD(LCD)
LCD supply current 50 +50 mA
P
tot
total power dissipation - 500 mW
P
o
output power - 100 mW
V
ESD
electrostatic discharge
voltage
HBM
[2]
- 2000 V
MM
[3]
- 200 V
I
lu
latch-up current
[4]
-100mA
T
stg
storage temperature
[5]
65 +150 C
T
amb
ambient temperature operating device 40 +85 C
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33

PCF8577CT/3,118

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Buy PCF8577CT/3,118
Manufacturer:
NXP Semiconductors
Description:
LCD Drivers LCD DRIVER 32/64SEG
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