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PCF8577CT/3,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33
PCF8577C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 10 October 2014 7 of 33
NXP Semiconductors
PCF8577C
LCD direct/duplex driver with I²C-bus interface
Duplex mode output waveforms are shown in Figure 5.
7.7 Display memory mapping
The mapping between the eight segment registers and the segment outputs S1 to S32 is
given in Table 5
and Table 6.
Since only one register bit per segment is needed in the direct drive mode, the BANK bit
allows swapping of display information. If BANK is set to logic 0, even bytes (BANK A) are
displayed; if BANK is set to logic 1 odd bytes (BANK B) are displayed. BP1 is always used
for the backplane output in the direct drive mode. In duplex mode, even bytes (BANK A)
correspond to backplane 1 (BP1) and odd bytes (BANK B) correspond to backplane 2
(BP2).
V
on(RMS)
= 0.791(V
DD
V
SS
); V
off(RMS)
= 0.354(V
DD
V
SS
).
Fig 5. Duplex mode display output waveforms
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%3 6[
9
''
9
''
9
''
9
66
9
''
9
66
9
''
9
66
9
''
9
66
9
''
9
66
9
66
9
66
9
''
9
66
9
66
9
''
9
66
9
''
9
66
9
''
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66
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''
9
66
DDD
PCF8577C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 10 October 2014 8 of 33
NXP Semiconductors
PCF8577C
LCD direct/duplex driver with I²C-bus interface
Mapping example: bit 0 of register 7 controls the LCD segment S25 if BANK bit is a
logic 1.
[1] Don’t care.
Mapping example: bit 7 of register 5 controls the LCD segment S24/BP2.
7.8 Power-on reset
At power-on reset the PCF8577C resets to a defined starting condition as follows:
1. Both backplane outputs are set to V
SS
in master mode; to 3-state in cascade mode
2. All segment outputs are set to V
SS
3. The segment byte registers and control register are cleared
4. The I
2
C-bus interface is initialized.
Table 5. Segment byte-segment driver mapping in direct drive mode
Mode Bank V2 V1 V0 Segment/
Bit/
Register
7
MSB
6 5 4 3 2 1 0
LSB
Backplane
0 0 0 0 0 0 S8 S7 S6 S5 S4 S3 S2 S1 BP1
0 1 0 0 1 1 S8 S7 S6 S5 S4 S3 S2 S1 BP1
0 0 0 1 0 2 S16 S15 S14 S13 S12 S11 S10 S9 BP1
0 1 0 1 1 3 S16 S15 S14 S13 S12 S11 S10 S9 BP1
0 0 1 0 0 4 S24 S23 S22 S21 S20 S19 S18 S17 BP1
0 1 1 0 1 5 S24 S23 S22 S21 S20 S19 S18 S17 BP1
0 0 1 1 0 6 S32 S31 S30 S29 S28 S27 S26 S25 BP1
0 1 1 1 1 7 S32 S31 S30 S29 S28 S27 S26 S25 BP1
Table 6. Segment byte-segment driver mapping in duplex mode
Mode Bank V2 V1 V0 Segment/
Bit/
Register
7
MSB
6 5 4 3 2 1 0
LSB
Backplane
1X
[1]
0 0 0 0 S8 S7 S6 S5 S4 S3 S2 S1 BP1
1X
[1]
0 0 1 1 S8 S7 S6 S5 S4 S3 S2 S1 BP2
1X
[1]
0 1 0 2 S16 S15 S14 S13 S12 S11 S10 S9 BP1
1X
[1]
0 1 1 3 S16 S15 S14 S13 S12 S11 S10 S9 BP2
1X
[1]
1 0 0 4 S24 S23 S22 S21 S20 S19 S18 S17 BP1
1X
[1]
1 0 1 5 S24 S23 S22 S21 S20 S19 S18 S17 BP2
1X
[1]
1 1 0 6 S32 S31 S30 S29 S28 S27 S26 S25 BP1
1X
[1]
1 1 1 7 S32 S31 S30 S29 S28 S27 S26 S25 BP2
PCF8577C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 10 October 2014 9 of 33
NXP Semiconductors
PCF8577C
LCD direct/duplex driver with I²C-bus interface
8. I
2
C-bus interface
8.1 Characteristics of the I
2
C-Bus
The I
2
C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the I
2
C-bus is not busy.
8.1.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
are interpreted as control signals.
8.1.2 START and STOP conditions
Both data and clock lines remain HIGH when the I
2
C-bus is not busy. A HIGH-to-LOW
transition of the data line, while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P).
8.1.3 System configuration
A device generating a message is a ‘transmitter’, a device receiving a message is the
‘receiver’. The device that controls the message is the ‘master’ and the devices which are
controlled by the master are the ‘slaves’.
Fig 6. Bit transfer
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GDWDYDOLG
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RIGDWD
DOORZHG
6'$
6&/
Fig 7. Definition of START and STOP conditions
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33

PCF8577CT/3,118

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Buy PCF8577CT/3,118
Manufacturer:
NXP Semiconductors
Description:
LCD Drivers LCD DRIVER 32/64SEG
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