Technical Note
7/16
BD9862MUV
www.rohm.com
2010.03 - Rev.A
© 2010 ROHM Co., Ltd. All rights reserved.
●System Description
BD9862MUV is a 3ch system power supply optimized for TFT liquid crystal displays.
Features of each channel are explained as follows
○CH1
This is a voltage mode switching regulator with a built-in high voltage-resistant output FET. Capable of high-speed operation
at the maximum switching frequency of 1.4MHz, and compatible with a high step-up ratio with Max Duty of 90%(typ.).
○CH2
It’s a PWM/PFM automatic switching control with a variable-voltage adding charge pump. Due to intermittent switching at
the time of PFM mode, the switching loss is reduced, so high efficiency is realized even in light load conditions. Moreover,
it is capable of operating at the maximum switching frequency of 700KHz because of a built-in high voltage resistant,
high-speed FET driver. In addition, it is equipped with an On Duty prediction function, so the output voltage ripple is
lowered considerably even at the time of PFM operation.Due to the built-in output discharge resistor (1kΩ typ.) and FET
phase compensation circuit, it can operate with two capacitors and two resistors.
○CH3
It includes a PWM/PFM automatic switching control, variable-voltage reversing charge pump controller. The control
method is the same as CH2.
●Block functional descriptions
・Error amplifier block
Detects the output voltage with INV terminal (NON3 terminal in case of CH3), amplifies the error between it and standard
voltage, and outputs from the FB terminal. The accuracy is ±1%(1.5% in case of CH2 & CH3).
・PWM(Pulse Width Modulation)Convertor block
The PWM convertor inputs the error detected by the error amplifier and outputs the PWM signal by comparing with a
saw-tooth wave.
・PWM/PFM Control Block
Due to the input of the PWM terminal, this block switches the CH2 & CH3 between the fixed PWM mode and the automatic
switching mode of PFM(Pulse Frequency Modulation)/PWM. At the time of PFM mode, the efficiency under a light load is
raised by controlling and making the lowest On Duty of PWM signal to be 7%(typ.) and reducing the number of switching times.
・LDO Block
This is a power supply to operate the internal circuit. In addition, it can be used as input of VIN2B. The output voltage is
3.5V(typ.), and the maximum load is 10mA. Moreover, due to a built-in UVLO, the release voltage is 2.5V(typ) and the
protective voltage is 2.4V(typ).
・Start-up Charge Pump Block
If REGOUT is ≦2.5V(typ.), then the ring oscillator, which operates at 500kHz or so, is started and the double charge
pump is operated. The clock pulse is controlled in such a way that the output voltage of this charge pump becomes
4.2V(typ.). Moreover, if REGOUT becomes more than 2.5V(typ.) (i.e. REGOUT＞2.5V(typ.)), then the clock is supplied
from the main OSC that creates a saw tooth wave. If the input voltage is usually more than 4.5V, then it is possible to
bypass the start-up circuit. (refer to the application example)
・OSC Block
It generates a saw-tooth wave and inputs it into the PWM comparator. It is possible to change the oscillating frequency by
means of the resistor RT. Due to RRT=120kΩ, the CH1 operates at 1MHz(typ.). The double charge pump, CH2 and CH3
operate at 1/2 of CH1 frequency.
・VREF Block
Generate the constant voltage that is standard inside the IC.
・UVLO Block
Performs the under voltage lockout by detecting the VBAT voltage with the UVLOSET terminal. The UVLO voltage can be
set by an external resistor.
・Soft Start Block
Due to sweep-starting of the standard voltage of the error amplifier at the ti
me of start-up, the excess input current & output
voltage is reduced. Moreover, only at the time of soft start, the CH2 is regarded as the resistance value of 150Ωtyp
between VIN2B & C2P and the CH3 is regarded as the resistance value of 60Ωtyp between VIN3 & C3P therefore the
input current is limited.
・Short-circuit protection of timer latch (SCP) block
Monitors the INV1 terminal and the error amplifier outputs of CH2 & CH3, and turns off the drivers of CH1~CH3 if a
short-circuit condition continues for more than a certain period of time. The timer latch time is counted by the CH1 internal
switching pulse. The counting is started when a short-circuit condition begins, ant the drivers are turned off when 131,072
is reached.
Example) if RRT=120kΩ, then 131072×(1/1[MHz])=131.072ms
・Thermal shutdown (TSD) block
Detects abnormal heat generation of the IC, stops the switching operation of all Ch and prevents the IC from thermal
overload. The detecting temperature is 175℃(typ), and the hysteresis is 10℃(typ).
