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CY7C026A-15AXI
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P24
CY7C026A
Document Number: 38-06046 Rev
. *J
Page 16 of 24
Figure 8. Sema
phore Read Af
ter Write Timing, Either Side
[32]
Figure 9. T
iming Diagram of Semaphore Cont
ention
[33, 34, 35]
Switching W
aveforms
(continued)
t
SOP
t
SAA
V
ALID ADRESS
V
ALID ADRESS
t
HD
DA
T
A
IN
VA
L
I
D
DA
T
A
OUT
VA
L
I
D
t
OHA
t
AW
t
HA
t
ACE
t
SOP
t
SCE
t
SD
t
SA
t
PWE
t
SWRD
t
DOE
WRITE CYCLE
READ CYCLE
OE
R/W
I/O
0
SEM
A
0
–A
2
ADDRESS MA
TCH
t
SPS
ADDRESS MA
TCH
R/W
L
SEM
L
R/W
R
SEM
R
A
0L
–A
2L
A
0R
–A
2R
Notes
32.
CE
= HIGH for the duration of the a
bove timing (both write and read cycle).
33.
I/O
0R
= I/O
0L
= LOW (request semaphore); CE
R
= CE
L
= HIGH.
34.
Semaphores are reset (available to both ports) at cycle st
art.
35.
If t
SPS
is violated, the semaphore is definitely obt
ained by one side or the other
, but which side gets the semaphore is unpredictable
.
CY7C026A
Document Number: 38-06046 Rev
. *J
Page 17 of 24
Figure 10. T
iming Diagram of Read with BUSY
(M/S
= HIGH)
[36]
Figure 1
1. W
rite Timing
with Busy Input (M
/S
= LOW)
Switching W
aveforms
(continued)
VA
L
I
D
t
DDD
t
WDD
ADDRESS MA
TCH
ADDRESS MA
TCH
R/W
R
DA
T
A
INR
DA
T
A
OUTL
t
WC
ADDRESS
R
t
PWE
VA
L
I
D
t
SD
t
HD
ADDRESS
L
t
PS
t
BLA
t
BHA
t
BDD
BUSY
L
t
PWE
R/W
BUSY
t
WB
t
WH
Note
36.
CE
L
= CE
R
= LOW
.
CY7C026A
Document Number: 38-06046 Rev
. *J
Page 18 of 24
Figure 12. Busy Timing Diagram No. 1 (CE
Arbitration)
[37]
Figure 13. B
usy Timing Diagram No. 2 (Ad
dress Arbitration)
[37]
Switching W
aveforms
(continued)
ADDRESS MA
TCH
t
PS
t
BLC
t
BHC
ADDRESS MA
TCH
t
PS
t
BLC
t
BHC
CE
R
V
alid First:
ADDRESS
L,R
BUSY
R
CE
L
CE
R
BUSY
L
CE
R
CE
L
ADDRESS
L,R
CE
L
V
alid First:
ADDRESS MA
TCH
t
PS
ADDRESS
L
BUSY
R
ADDRESS MISMA
TCH
t
RC
or t
WC
t
BLA
t
BHA
ADDRESS
R
ADDRESS MA
TCH
ADDRESS MISMA
TCH
t
PS
ADDRESS
L
BUSY
L
t
RC
or t
WC
t
BLA
t
BHA
ADDRESS
R
Right Address V
alid First:
Left Address V
alid
First:
Note
37.
If t
PS
is violated, the busy signal is as
serted on one side or the other
, but there is no guarantee to which side BUSY
is asserted.
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P24
CY7C026A-15AXI
Mfr. #:
Buy CY7C026A-15AXI
Manufacturer:
Cypress Semiconductor
Description:
SRAM 256Kb 15ns 16K x 16 Dual Port SRAM
Lifecycle:
New from this manufacturer.
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