CY7C026A
Document Number: 38-06046 Rev. *J Page 7 of 24
Interrupts
The upper two memory locations may be used for message
passing. The highest memory location (3FFF) is the mailbox for
the right port and the second highest memory location (3FFE) is
the mailbox for the left port. When one port writes to the other
port’s mailbox, an interrupt is generated to the owner. The
interrupt is reset when the owner reads the contents of the
mailbox. The message is user defined.
Each port can read the other port’s mailbox without resetting the
interrupt. The active state of the busy signal (to a port) prevents
the port from setting the interrupt to the winning port. Also, an
active busy to a port prevents that port from reading its own
mailbox and, thus, resetting the interrupt to it.
If an application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin.
The operation of the interrupts and their interaction with Busy are
summarized in Table 2.
Busy
The CY7C026A provides on-chip arbitration to resolve
simultaneous memory location access (contention). If both ports’
CEs are asserted and an address match occurs within t
PS
of
each other, the busy logic determines which port has access. If
t
PS
is violated, one port definitely gains permission to the
location, but it is not predictable which port gets that permission.
BUSY is asserted t
BLA
after an address match or t
BLC
after CE
is taken LOW.
Master/Slave
A M/S pin is provided to expand the word width by configuring
the device as either a master or a slave. The BUSY
output of the
master is connected to the BUSY
input of the slave. This allows
the device to interface to a master device with no external
components. Writing to slave devices must be delayed until after
the BUSY
input has settled (t
BLC
or t
BLA
), otherwise, the slave
chip may begin a write cycle during a contention situation. When
tied HIGH, the M/S
pin allows the device to be used as a master
and, therefore, the BUSY
line is an output. BUSY can then be
used to send the arbitration outcome to a slave.
Table 2. Interrupt Operation Example (Assumes BUSY
L
= BUSY
R
= HIGH)
Function
Left Port Right Port
R/W
L
CE
L
OE
L
A
0L–13L
INT
L
R/W
R
CE
R
OE
R
A
0R–13R
INT
R
Set right INT
R
flag LLX 3FFF XXXX X L
[2]
Reset right INT
R
flagXXX X XXLL 3FFF H
[3]
Set left INT
L
flag X X X X L
[3]
LLX 3FFE X
Reset left INT
L
flag X L L 3FFE H
[2]
XXXXX
Notes
2. If BUSY
R
= L, then no change.
3. If BUSY
L
= L, then no change.
CY7C026A
Document Number: 38-06046 Rev. *J Page 8 of 24
Semaphore Operation
The CY7C026A provides eight semaphore latches, which are
separate from the dual-port memory locations. Semaphores are
used to reserve resources that are shared between the two ports.
The state of the semaphore indicates that a resource is in use.
For example, if the left port wants to request a given resource, it
sets a latch by writing a zero to a semaphore location. The left
port then verifies its success in setting the latch by reading it.
After writing to the semaphore, SEM
or OE must be deasserted
for t
SOP
before attempting to read the semaphore. The
semaphore value is available t
SWRD
+ t
DOE
after the rising edge
of the semaphore write. If the left port was successful (reads a
zero), it assumes control of the shared resource, otherwise
(reads a one) it assumes the right port has control and continues
to poll the semaphore. When the right side has relinquished
control of the semaphore (by writing a one), the left side
succeeds in gaining control of the semaphore. If the left side no
longer requires the semaphore, a one is written to cancel its
request.
Semaphores are accessed by asserting SEM
LOW. The SEM
pin functions as a chip select for the semaphore latches (CE
must remain HIGH during SEM LOW). A
0–2
represents the
semaphore address. OE
and R/W are used in the same manner
as a normal memory access. When writing or reading a
semaphore, the other address pins have no effect.
When writing to the semaphore, only I/O
0
is used. If a zero is
written to the left port of an available semaphore, a one appears
at the same semaphore address on the right port. That
semaphore can now only be modified by the side showing zero
(the left port in this case). If the left port now relinquishes control
by writing a one to the semaphore, the semaphore is set to one
for both sides. However, if the right port had requested the
semaphore (written a zero) while the left port had control, the
right port would immediately own the semaphore as soon as the
left port released it. Table 3 on page 8 shows sample semaphore
operations.
When reading a semaphore, all sixteen/eighteen data lines
output the semaphore value. The read value is latched in an
output register to prevent the semaphore from changing state
during a write from the other port. If both ports attempt to access
the semaphore within t
SPS
of each other, the semaphore is
definitely obtained by one side or the other, but there is no
guarantee which side controls the semaphore.
Table 3. Semaphore Operation Example
Function I/O
0
I/O
15
Left I/O
0
I/O
15
Right Status
No action 1 1 Semaphore free
Left port writes 0 to semaphore 0 1 Left port has semaphore token
Right port writes 0 to semaphore 0 1 No change. Right side has no write access to semaphore
Left port writes 1 to semaphore 1 0 Right port obtains semaphore token
Left port writes 0 to semaphore 1 0 No change. Left port has no write access to semaphore
Right port writes 1 to semaphore 0 1 Left port obtains semaphore token
Left port writes 1 to semaphore 1 1 Semaphore free
Right port writes 0 to semaphore 1 0 Right port has semaphore token
Right port writes 1 to semaphore 1 1 Semaphore free
Left port writes 0 to semaphore 0 1 Left port has semaphore token
Left port writes 1 to semaphore 1 1 Semaphore free
CY7C026A
Document Number: 38-06046 Rev. *J Page 9 of 24
Maximum Ratings
Exceeding maximum ratings
[4]
may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature
with power applied ................................... –55
°C to +125 °C
Supply voltage to ground potential ..............–0.3 V to +7.0 V
DC voltage applied to outputs
in High Z state .............................................–0.5 V to +7.0 V
DC input voltage
[5]
.....................................–0.5 V to + 7.0 V
Output current into outputs (LOW) .............................20 mA
Static discharge voltage .......................................... >2001 V
Latch-up current .................................................... >200 mA
Operating Range
Range
Ambient Temperature
V
CC
Commercial 0 °C to +70 °C 5 V 10%
Industrial –40 °C to +85 °C 5 V 10%
Electrical Characteristics
Over the Operating Range
Parameter Description
CY7C026A
Unit-15 -20
Min Typ Max Min Typ Max
V
OH
Output HIGH voltage
(V
CC
= Min., I
OH
= –4.0 mA)
2.4– –2.4– V
V
OL
Output LOW voltage
(V
CC
= Min., I
OH
= +4.0 mA)
–0.4–0.4V
V
IH
Input HIGH voltage 2.2 2.2 V
V
IL
Input LOW voltage 0.8 0.8 V
I
OZ
Output leakage current –10 10 –10 10 A
I
CC
Operating current
(V
CC
= Max, I
OUT
= 0 mA)
outputs disabled
Commercial 190 285 180 275 mA
Industrial 215 305 mA
I
SB1
Standby current
(Both ports TTL level)
CE
L
& CE
R
V
IH
, f = f
MAX
Commercial 50 70 45 65 mA
Industrial 65 95 mA
I
SB2
Standby current
(One port TTL level)
CE
L
| CE
R
V
IH
, f = f
MAX
Commercial 120 180 110 160 mA
Industrial 135 205 mA
I
SB3
Standby current
(Both port CMOS level)
CE
L
& CE
R
V
CC
0.2 V, f = 0
Commercial 0.05 0.5 0.05 0.5 mA
Industrial 0.05 0.5 mA
I
SB4
Standby current
(One port CMOS level)
CE
L
| CE
R
V
IH
, f = f
MAX
[6]
Commercial 110 160 100 140 mA
Industrial 125 175 mA
Notes
4. The voltage on any input or I/O pin cannot exceed the power pin during power up.
5. Pulse width < 20 ns.
6. f
MAX
= 1/t
RC
= All inputs cycling at f = 1/t
RC
(except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby I
SB3
.

CY7C026A-15AXI

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
SRAM 256Kb 15ns 16K x 16 Dual Port SRAM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet