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XC2C32A-4CP56C

P1-P3P4-P6P7-P9P10-P12P13-P14
XC2C32A CoolRunner-II CPLD
DS310 (v2.1) November 6, 2008 www.xilinx.com 7
Product Specification
R
Switching Characteristics AC Test Circuit
I/O Standard Time Adder Delays 2.5V CMOS
T
IN25
Standard input adder - 0.5 - 0.6 ns
T
HYS25
Hysteresis input adder - 3.0 - 4.0 ns
T
OUT25
Output adder - 0.6 - 0.7 ns
T
SLEW25
Output slew rate adder - 4.0 - 5.0 ns
I/O Standard Time Adder Delays 3.3V CMOS/TTL
T
IN33
Standard input adder - 0.5 - 0.6 ns
T
HYS33
Hysteresis input adder - 3.0 - 4.0 ns
T
OUT33
Output adder - 1.0 - 1.2 ns
T
SLEW33
Output slew rate adder - 4.0 - 5.0 ns
Notes:
1. 1.5 ns input pin signal rise/fall.
Internal Timing Parameters (Continued)
Symbol Parameter
(1)
-4 -6
UnitsMin. Max. Min. Max.
Figure 2: Derating Curve for T
PD
Number of Outputs Switching
12 4 8 16
3.0
4.0
5.0
V
CC
= V
CCIO
= 1.8V @ 25
o
C
T
PD2
(ns)
5.5
4.5
3.5
DS091_02_112002
Figure 3: AC Load Circuit
R
1
V
CC
C
L
R
2
Device
Under Test
Output Type
LVTTL33
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
C
L
includes test fixtures and probe capacitance.
1.5 nsec maximum rise/fall times on inputs.
R
1
268Ω
275Ω
188Ω
112.5Ω
150Ω
R
2
235Ω
275Ω
188Ω
112.5Ω
150Ω
C
L
35 pF
35 pF
35pF
35pF
35pF
DS310_03_102108
Test Point
XC2C32A CoolRunner-II CPLD
8 www.xilinx.com DS310 (v2.1) November 6, 2008
Product Specification
R
Typical I/O Output Curves
Figure 4: Typical I/V Curve for XC2C32A
VO (Output Volts)
XC32_VoIo_all_0403
IO (Output Current mA)
0
0
40
10
50
20
30
60
3.02.52.01.51.0.5 3.5
3.3V
1.5V
1.8V
2.5V
Iol
Pin Descriptions
Function Block Macrocell QFG32 PC44
(1)
VQ44 CP56 I/O Bank
1 1 44 38 F1 Bank 2
1 2 43 37 E3 Bank 2
1 3 42 36 E1 Bank 2
1(GTS1) 4 3 40 34 D1 Bank 2
1(GTS0) 5 2 39 33 C1 Bank 2
1(GTS3) 6 1 38 32 A3 Bank 2
1(GTS2) 7 32 37 31 A2 Bank 2
1(GSR)8 313630B1Bank 2
1 9 303529A1Bank 2
1 10 29 34 28 C4 Bank 2
1 11283327C5Bank 2
1 12242923C8Bank 2
113 2822A10Bank 2
1 14232721B10Bank 2
1 15 26 20 C10 Bank 2
1 16 25 19 E8 Bank 2
215139G1Bank 1
2 2 2 40 F3 Bank 1
2 3 3 41 H1 Bank 1
2 4 4 42 G3 Bank 1
2(GCK0) 5 6 5 43 J1 Bank 1
2(GCK1) 6 7 6 44 K1 Bank 1
2(GCK2) 7 8 7 1 K2 Bank 1
XC2C32A CoolRunner-II CPLD
DS310 (v2.1) November 6, 2008 www.xilinx.com 9
Product Specification
R
XC2C32A Global, JTAG, Power/Ground, and No Connect Pins
2 8 9 8 2 K3 Bank 1
2 9 10 9 3 H3 Bank 1
2 10 11 5 K5 Bank 1
211 126H5Bank 1
21213148H8Bank 1
2 13171812K8Bank 1
2 14181913H10Bank 1
2 15192014G10Bank 1
2 16 22 16 F10 Bank 1
Notes:
1. This is an obsolete package type. It remains here for legacy support only.
2. GTS = global output enable, GSR = global set reset, GCK = global clock.
3. GTS, GSR, and GCK pins can also be used for general purpose I/O.
Pin Type QFG32 PC44
(1)(2)
VQ44
(2)
CP56
(2)
TCK 16 17 11 K10
TDI 14 15 9 J10
TDO 25 30 24 A6
TMS 15 16 10 K9
Input Only 22 (bank 2) 24 (bank 2) 18 (bank 2) D10 (bank 2)
V
CCAUX
(JTAG supply voltage) 4 41 35 D3
Power internal (V
CC
)
Power bank 1 I/O (V
CCIO1
)
Power bank 2 I/O (V
CCIO2
)
20 21 15 G8
12 13 7 H6
27 32 26 C6
Ground 11, 21, 26 10,23,31 4,17,25 H4, F8, C7
No connects - - K4, K6, K7, H7,
E10, A7, A9, D8,
A5, A8, A4, C3
Total user I/O (includes dual function pins) 21 33 33 33
Notes:
1. This is an obsolete package type. It remains here for legacy support only.
2. All packages pin compatible with larger macrocell densities.
Pin Descriptions (Continued)
Function Block Macrocell QFG32 PC44
(1)
VQ44 CP56 I/O Bank
P1-P3P4-P6P7-P9P10-P12P13-P14

XC2C32A-4CP56C

Mfr. #:
Buy XC2C32A-4CP56C
Manufacturer:
Xilinx
Description:
CPLD - Complex Programmable Logic Devices
Lifecycle:
New from this manufacturer.
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