LTM4603/LTM4603-1
7
4603fb
pin Functions
(See Package Description for Pin Assignment)
V
IN
(Bank 1): Power Input Pins. Apply input voltage be-
tween these pins and PGND pins. Recommend placing
input decoupling capacitance directly between V
IN
pins
and PGND pins.
V
OUT
(Bank 3): Power Output Pins. Apply output load
between these pins and PGND pins. Recommend placing
output decoupling capacitance directly between these pins
and PGND pins. See Figure 15.
PGND (Bank 2): Power ground pins for both input and
output returns.
V
OSNS
(Pin M12): (–) Input to the Remote Sense Ampli-
fier. This pin connects to the ground remote sense point.
The remote sense amplifier is used for V
OUT
≤ 3.3V. Tie
to INTV
CC
if not used.
NC1 (Pin M12): No internal connection on the LTM4603-1.
V
OSNS
+
(Pin J12): (+) Input to the Remote Sense Ampli-
fier. This pin connects to the output remote sense point.
The remote sense amplifier is used for V
OUT
≤ 3.3V. Tie
to ground if not used.
NC2 (Pin J12): No internal connection on the LTM4603-1.
DIFFV
OUT
(Pin K12): Output of the Remote Sense Ampli-
fier. This pin connects to the V
OUT_LCL
pin. Leave floating
if remote sense amplifier is not used.
NC3 (Pin K12): No internal connection on the LTM4603-1.
DRV
CC
(Pin E12): This pin normally connects to INTV
CC
for powering the internal MOSFET drivers. This pin can
be biased up to 6V from an external supply with about
50mA capability, or an external circuit shown in Figure
16. This improves efficiency at the higher input voltages
by reducing power dissipation in the module.
INTV
CC
(Pin A7): This pin is for additional decoupling of
the 5V internal regulator.
PLLIN (Pin A8): External Clock Synchronization Input
to the Phase Detector. This pin is internally terminated
to SGND with a 50k resistor. Apply a clock with a high
level above 2V and below INTV
CC
. See the Applications
Information section.
TRACK/SS (Pin A9): Output Voltage Tracking and Soft-
Start Pin. When the module is configured as a master
output, then a soft-start capacitor is placed on this pin
to ground to control the master ramp rate. A soft-start
capacitor can be used for soft-start turn on as a stand
alone regulator. Slave operation is performed by putting
a resistor divider from the master output to ground, and
connecting the center point of the divider to this pin. See
the Applications Information section.
MPGM (Pin A12): Programmable Margining Input. A re-
sistor from this pin to ground sets a current that is equal
to 1.18V/R. This current multiplied by 10kW will equal a
value in millivolts that is a percentage of the 0.6V refer-
ence voltage. See Applications Information. To parallel
LTM4603s, each requires an individual MPGM resistor.
Do not tie MPGM pins together.
MARG1
DRV
CC
V
FB
PGOOD
SGND
V
OSNS
+
(NC2, LTM4603-1)
DIFFV
OUT
(NC3, LTM4603-1)
V
OUT_LCL
V
OSNS
(NC1, LTM4603-1)
V
IN
BANK 1
PGND
BANK 2
A
B
C
D
E
F
G
H
J
K
L
M
V
OUT
BANK 3
f
SET
MARG0
RUN
COMP
MPGM
PLLIN
INTV
CC
TRACK/SS
1 2 3 4 5 6 7
TOP VIEW
8 9 10 11 12
LTM4603/LTM4603-1
8
4603fb
f
SET
(Pin B12): Frequency Set Internally to 1MHz. An
external resistor can be placed from this pin to ground
to increase frequency. See the Applications Information
section for frequency adjustment.
V
FB
(Pin F12): The Negative Input of the Error Ampli-
fier. Internally, this pin is connected to V
OUT_LCL
with a
60.4k precision resistor. Different output voltages can be
programmed with an additional resistor between V
FB
and
SGND pins. See the Applications Information section.
MARG0 (Pin C12): This pin is the LSB logic input for the
margining function. Together with the MARG1 pin it will
determine if margin high, margin low or no margin state
is applied. The pin has an internal pull-down resistor of
50k. See the Applications Information section.
MARG1 (Pin D12): This pin is the MSB logic input for the
margining function. Together with the MARG0 pin it will
determine if margin high, margin low or no margin state
is applied. The pin has an internal pull-down resistor of
50k. See the Applications Information section.
SGND (Pin H12): Signal Ground. This pin connects to
PGND at output capacitor point.
COMP (Pin A11): Current Control Threshold and Error
Amplifier Compensation Point. The current comparator
threshold increases with this control voltage. The voltage
ranges from 0V to 2.4V with 0.7V corresponding to zero
sense voltage (zero current).
PGOOD (Pin G12): Output Voltage Power Good Indicator.
Open-drain logic output that is pulled to ground when the
output voltage is not within ±10% of the regulation point,
after a 25µs power bad mask timer expires.
RUN (Pin A10): Run Control Pin. A voltage above 1.9V
will turn on the module, and when below 1V, will turn
off the module. A programmable UVLO function can be
accomplished by connecting to a resistor divider from
V
IN
to ground. See Figure 1. This pin has a 5.1V Zener to
ground. Maximum pin voltage is 5V. Limit current into the
RUN pin to less than 1mA.
V
OUT_LCL
(Pin L12): V
OUT
connects directly to this pin to
bypass the remote sense amplifier, or DIFFV
OUT
connects
to this pin when the remote sense amplifier is used.
V
OUT_LCL
can be connected to V
OUT
on the LTM4603-1.
V
OUT
is internally connected to V
OUT_LCL
through 50W in
the LTM4603-1.
pin Functions
(See Package Description for Pin Assignment)
LTM4603/LTM4603-1
9
4603fb
Figure 1. Simplified LTM4603/LTM4603-1 Block Diagram
siMpliFieD block DiagraM
Decoupling requireMents
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
C
IN
External Input Capacitor Requirement
(V
IN
= 4.5V to 20V, V
OUT
= 1.5V)
I
OUT
= 6A 20 µF
C
OUT
External Output Capacitor Requirement
(V
IN
= 4.5V to 20V, V
OUT
= 1.5V)
I
OUT
= 6A 100 200 µF
T
A
= 25°C, V
IN
= 12V. Use Figure 1 configuration.
+
INTERNAL
COMP
SGND
COMP
PGOOD
UVLO
FUNCTION
RUN
V
IN
V
OUT_LCL
>1.9V = ON
<1V = OFF
MAX = 5V
MARG1
MARG0
MPGM
PLLIN
C
SS
INTV
CC
DRV
CC
TRACK/SS
V
FB
f
SET
50k
R2
R1
33.2k
R
SET
40.2k
50k
60.4k
V
OUT
1M
(50Ω, LTM4603-1)
5.1V
ZENER
POWER CONTROL
Q1
V
IN
4.5V TO 20V
V
OUT
1.5V
6A
Q2
10k
10k
10k50k
10k
INTV
CC
+
22µF
1.5µF
C
IN
+
C
OUT
PGND
V
OSNS
NOT INCLUDED
IN THE LTM4603-1
V
OSNS
= NC1
V
OSNS
+
= NC2
DIFFV
OUT
= NC3
V
OSNS
+
DIFFV
OUT
4603 F01
4.7µF
H

LTM4603IV#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 20V, 6A Step-down Module Regulator with PLL input
Lifecycle:
New from this manufacturer.
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