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A7001CMHN1/T1AGCEL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
A700X_FAM_SDS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product short data sheet
Rev. 3.1 — 5 July 2013
202031 10 of 18
NXP Semiconductors
A700x family
Secure authentication microcontroller
[1] To configure JCOP V2.4.2 R1 to be application backward compatible contact NXP Semiconductors Customer Application Support
(CAS).
5.1.1 Samples and final products
Section 5.1.2, Section 5.1.3 and Section 5.1.4 give details of how to order samples and
final products.
5.1.2 Ordering A700x family samples
Samples in HVQFN32 package can be ordered from NXP Semiconductors.
Note that NXP Semiconductors can provide up to 10 pieces free of charge. Larger
quan
tities have to be ordered separately. Valid NDA has to be in place before samples are
shipped.
Contact your local NXP Semiconductors repre
sentative for further information.
5.1.3 Ordering JCOP products
NXP Semiconductors has created various product configurations which are available for
ordering. For a complete list of orderable A700x product types and part numbers, contact
your local NXP Semiconductors representative.
5.1.4 JCOP tools
JCOP tools provide Integrated Development Environment (IDE) based on the ECLIPSE
framework and specific JCOP product family through the JCOP tools plug-in.
Contact your local NXP Semiconductors repres
entative for further information on JCOP
tools (plug-in) availability.
Table 5. JCOP V2.4.2 feature table
Product type Java
Card
Global
Platform
VGP
configurable
1, 2, 3
Applet backward
compatible VGP 2.0.1
[1]
Applet
loading
APDU
Buffer
IO configure
and control
API
JCOP V2.4.2 R1 3.0.1 2.1.1 3 yes yes 1462 bytes
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx
xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x
A700X_FAM_SDS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product short data sheet
Rev. 3.1 — 5 July 2013
202031 11 of 18
NXP Semiconductors
A700x family
Secure authentication microcontroller
6. Block diagram
(1) For more details, see Ref. 4
(2) For more details, see Ref. 5
(3) ISO/IEC 7816 interface not available on A7001/2
(4) ISO/IEC 14443 A interface only available on A7005/6
(5) Depends on configuration of JCOP 2.4.2 R1
Fig 1. A700x family block diagram
APPLICATION
LAYER
APPLET n
GLOBAL
PLATFORM
2.1.1
OTHER
SERVICES
SECURE BOX
ISO/IEC 14443 T=CL
(4)
MIFARE
HARDWARE
(5)
EEPROM
SECURE_MX51
CPU
ROM ACMRAM
INTERFACE
MEMORY
MANAGEMENT
UNIT
(MMU)
PKI
COPROCESSOR
FameXE
AES
COPROCESSOR
TRIPLE-DES
COPROCESSOR
VDD VSS SDA/IO1
(3)
SCL/IO2
(3)
LA
(4)
RST_N
PVDD/CLK
(3)
HARDWARE
LAYER
PLATFORM
A700x
ISO/IEC 7816
T=0, T=1
(3)
SCI
2
C PROTOCOL
(2)
JAVA CARD VIRTUAL MACHINE
(JCVM)
I/O NETWORK
COMMUNICATION
TRANSACTION
MANAGEMENT
APPLET
MANAGEMENT
SYSTEM CLASSES
INSTALLER
JAVA CARD
RUNTIME
ENVIRONMENT
3.0.1 CLASSIC
(1)
CARD
OPERATING
SYSTEM
LAYER
JCOP V2.4.2
EXTENSIONS
FRAMEWORK CLASSES APIs
(JAVA CARD 3.0.1 CLASSIC APIs)
MIFARE (MULTI-)
APPLICATION
(5)
MIFARE
PROTOCOL
(5)
MIFARE
IMPLEMENTATION
(5)
(incl. MIFARE
SECURITY)
APPLET 1APPLETS APPLET 2
LB
(4)
IO3
aaa-007775
A700X_FAM_SDS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product short data sheet
Rev. 3.1 — 5 July 2013
202031 12 of 18
NXP Semiconductors
A700x family
Secure authentication microcontroller
7. Limiting values
[1] MIL Standard 883-D method 3015; human body model; C = 100 pF, R = 1.5 k; T
amb
= 25 C to +85 C.
[2] Depending on appropriate thermal resistance of the package.
[3] Depending on delivery type, refer to NXP Semiconductor
s General Specification for 8” Wafers and to NXP
Semiconductors Contact & Dual Interface Chip Card Module Specificatio
n.
8. Application information
Figure 2 shows a typical application diagram. It shows how the pins of the A700x family
are applied to operate the IC in an I
2
C system as an I
2
C slave device. In this system, an
individual reset control is not supported. The hardware reset is executed at power-up time
(power-on reset).
Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
VSS (ground = 0
V).
Symbol Parameter Conditions Min Max Unit
V
DD
supply voltage 0.5 +6.0 V
V
I
input voltage any signal pad 0.5 V
DD
+ 0.5 V
I
I
input current pad SDA, SCL or
IO3
- 15.0 mA
I
O
output current pad SDA, SCL or
IO3
- 15.0 mA
I
lu
latch-up current V
I
< 0 V
or V
I
> V
DD
- 100 mA
V
ESD
electrostatic discharge voltage pads VDD, VSS,
SDA, SCL, IO3
[1]
- 4.0 kV
P
tot
total power dissipation
[2]
- 1 W
T
stg
storage temperature
[3]
- - C
Fig 2. System overview supporting Power-on Reset
001aao366
10 kΩ
PUPU
10 kΩ
SCL SDA VSS VDD
VDD
VSS
SDA
SCL
VDD VSS PVDD
HOST CONTROLLER
A700x
RST_N SDA SCL
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

A7001CMHN1/T1AGCEL

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Buy A7001CMHN1/T1AGCEL
Manufacturer:
NXP Semiconductors
Description:
Security ICs / Authentication ICs SecureAuthentication microcontroller
Lifecycle:
New from this manufacturer.
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