IDT
™
/ ICS
™
SAS/SATA CLOCK GENERATOR 9 ICS843241BG REV. A AUGUST 20, 2008
ICS843241
FEMTOCLOCKS™ SAS/SATA CLOCK GENERATOR
APPLICATION INFORMATION
FIGURE 1. CRYSTAL INPUt INTERFACE
CRYSTAL INPUT INTERFACE
The ICS843241 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 1
below were determined using a 25MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
The optimum C1 and C2 values can be slightly adjusted for
different board layouts.
XTAL_IN
XTAL_OUT
X1
18pF Parallel Crystal
C1
27p
C2
27p
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in
Figure 2.
The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to
half swing in order to prevent signal interference with the power
rail and to reduce noise. This configuration requires that the output
FIGURE 2. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω. This can also be accomplished by removing
R1 and making R2 50Ω.
R2
Zo = 50
VDD
Ro
Zo = Ro + Rs
R1
VDD
XTA L _I N
XTA L _OU T
.1uf
Rs
