©2001 Fairchild Semiconductor Corporation HUF75307T3ST Rev. B
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, T
J(MAX)
, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, P
D(MAX)
,
in an application. Therefore the application’s ambient
temperature, T
A
(
o
C), and thermal resistance R
θJA
(
o
C/W)
must be reviewed to ensure that T
J(MAX)
is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
In using surface mount devices such as the SOT-223
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of the
P
D(MAX)
is complex and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 20
defines the R
θJA
for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse applications
can be evaluated using the Fairchild device Spice thermal
model or manually utilizing the normalized maximum
transient thermal impedance curve.
Displayed on the curve are the three R
θJA
values listed in
the Electrical Specifications table. The three points were
chosen to depict the compromise between the copper board
area, the thermal resistance and ultimately the power
dissipation, P
D(MAX)
. Thermal resistances corresponding to
other component side copper areas can be obtained from
Figure 20 or by calculation using Equation 2. The area, in
square inches is the top copper area including the gate and
source pads.
FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
Test Circuits and Waveforms
(Continued)
V
GS
R
L
R
GS
DUT
+
-
V
DD
V
DS
V
GS
t
ON
t
d(ON)
t
r
90%
10%
V
DS
90%
10%
t
f
t
d(OFF)
t
OFF
90%
50%
50%
10%
PULSE WIDTH
V
GS
0
0
(EQ.
P
DMAX()
T
JMAX()
T
A
–()
R
θJA
--------------------------------------------=
FIGURE 20. THERMAL RESISTANCE vs MOUNTING PAD
AREA
50
100
150
200
0.01 0.1 1.
147
o
C/W - 0.026in
2
R
θJA
= 75.9 -19.3 ln(AREA)
AREA, TOP COPPER AREA (in
2
)
R
θJA
(
o
C/W)
128
o
C/W - 0.068in
2
110
o
C/W - 0.171in
2
(EQ.
R
θJA
75.9 19.3 Area()ln×–=
HUF75307T3ST
