IDT5V41065
2 OUTPUT PCIE GEN1/2 SYNTHESIZER
IDT®
2 OUTPUT PCIE GEN1/2 SYNTHESIZER 4
IDT5V41065 APRIL 17, 2017
Applications Information
External Components
A minimum number of external components are required for
proper operation.
Decoupling Capacitors
Decoupling capacitors of 0.01F should be connected
between each VDD pin and the ground plane, as close to
the VDD pin as possible. Do not share ground vias between
components. Route power from power source through the
capacitor pad and then into ICS pin.
Crystal
A 25 MHz fundamental mode parallel resonant crystal
should be used. This crystal must have less than 300 ppm
of error across temperature in order for the IDT5V41065 to
meet PCI Express specifications.
Crystal Capacitors
Crystal capacitors are connected from pins X1 to ground
and X2 to ground to optimize the accuracy of the output
frequency.
C
L
= Crystal’s load capacitance in pF
Crystal Capacitors (pF) = (C
L
- 8) * 2
For example, for a crystal with a 16 pF load cap, each
external crystal cap would be 16 pF. (16-8)*2=16.
Current Source (Iref) Reference Resistor - R
R
If board target trace impedance (Z) is 50, then R
R
= 475
(1%), providing IREF of 2.32 mA. The output current (I
OH
) is
equal to 6*IREF.
Output Termination
The PCI-Express differential clock outputs of the
IDT5V41065 are open source drivers and require an
external series resistor and a resistor to ground. These
resistor values and their allowable locations are shown in
detail in the PCI-Express Layout Guidelines section.
The IDT5V41065 can also be configured for LVDS
compatible voltage levels. See the LVDS Compatible
Layout Guidelines section.
Output Structures
General PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1. Each 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible.
2. No vias should be used between decoupling capacitor
and VDD pin.
3. The PCB trace to VDD pin should be kept as short as
possible, as should the PCB trace to the ground via.
Distance of the ferrite bead and bulk decoupling from the
device is less critical.
4. An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (any ferrite beads and bulk decoupling capacitors can
be mounted on the back). Other signal traces should be
routed away from the IDT5V41065.This includes signal
traces just underneath the device, or on layers adjacent to
the ground plane layer used by the device.
R
R
475
6*IREF
=2.3 mA
IREF
See Output Termination
Sections - Pages 3 ~ 5
IDT5V41065
2 OUTPUT PCIE GEN1/2 SYNTHESIZER
IDT®
2 OUTPUT PCIE GEN1/2 SYNTHESIZER 5
IDT5V41065 APRIL 17, 2017
Layout Guidelines
Common Recommendations for Differential Routing Dimension or Value Unit Figure
L1 length, route as non-coupled 50ohm trace 0.5 max inch 1
L2 length, route as non-coupled 50ohm trace 0.2 max inch 1
L3 length, route as non-coupled 50ohm trace 0.2 max inch 1
Rs 33 ohm 1
Rt 49.9 ohm 1
Down Device Differential Routing
L4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max inch 1
L4 length, route as coupled stripline 100ohm differential trace 1.8 min to 14.4 max inch 1
Differential Routing to PCI Express Connector
L4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max inch 2
L4 length, route as coupled stripline 100ohm differential trace 0.225 min to 12.6 max inch 2
SRC Reference Clock
HCSL Output Buffer
L1
L1'
Rs
L2
L2'
Rs
L4'
L4
L3L3'
Rt Rt
PCI Express
Down Device
REF_CLK Input
Figure 1: Down Device Routing
HCSL Output Buffer
L1
L1'
Rs
L2
L2'
Rs
L4'
L4
L3L3'
Rt Rt
PCI Express
Add-in Board
REF_CLK Input
Figure 2: PCI Express Connector Routing
IDT5V41065
2 OUTPUT PCIE GEN1/2 SYNTHESIZER
IDT®
2 OUTPUT PCIE GEN1/2 SYNTHESIZER 6
IDT5V41065 APRIL 17, 2017
HCSL Output Buffer
L1
L1'
R1b
L2
L2'
R1a
L4'
L4
L3
R2a R2b
Down Device
REF_CLK Input
Figure 3
L3'
R3 R4
Component Value Note
R5a, R5b 8.2K 5%
R6a, R6b 1K 5%
Cc 0.1 µF
Vcm 0.350 volts
Cable Connected AC Coupled Application (figure 4)
PCIe Device
REF_CLK Input
Figure 4
R5a
L4'
L4
3.3 Volts
R5b
R6a R6b
Cc
Cc

5V41065PGG8

Mfr. #:
Manufacturer:
IDT
Description:
Clock Generators & Support Products PCIE GEN2 SSCG
Lifecycle:
New from this manufacturer.
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