IDT5V41065
2 OUTPUT PCIE GEN1/2 SYNTHESIZER
IDT®
2 OUTPUT PCIE GEN1/2 SYNTHESIZER 9
IDT5V41065 APRIL 17, 2017
AC Electrical Characteristics - CLK0/CLK1, CLK0/CLK1
Unless stated otherwise, VDD=3.3 V ±5%, Ambient Temperature -40 to +85C
Note 1: Test setup is R
S
=33R
P
=50 with C
L
=2 pF, Rr = 475 (1%).
Note 2: Measurement taken from a single-ended waveform.
Note 3: Measurement taken from a differential waveform.
Note 4: Measured at the crossing point where instantaneous voltages of both CLK and CLK
are equal.
Note 5: CLK pins are tri-stated when OE is low asserted. CLK is driven differential when OE is high.
Electrical Characteristics - Differential Phase Jitter
Note 1. Guaranteed by design and characterization, not 100% tested in production.
Note 2. See http://www.pcisig.com for complete specs.
Note 3: Applies to 100MHz, spread off and 0.5% down spread only.
Parameter Symbol Conditions Min. Typ. Max. Units
Input Frequency 25 MHz
Output Frequency HCSL termination 25 200 MHz
LVDS termination 25 100 MHz
Output High Voltage
1,2
V
OH
HCSL 850 mV
Output Low Voltage
1,2
V
OL
HCSL -150 mV
Crossing Point Voltage
1,2
Absolute 250 550 mV
Crossing Point Voltage
1,2,4
Variation over all edges 140 mV
Jitter, Cycle-to-Cycle
1,3
100 ps
Frequency Synthesis Error All outputs 0 ppm
Modulation Frequency Spread spectrum 30 32.9 33 kHz
Rise Time
1,2
t
OR
From 0.175 V to 0.525 V 175 700 ps
Fall Time
1,2
t
OF
From 0.525 V to 0.175 V 175 700 ps
Rise/Fall Time Variation
1,2
125 ps
Output to Output Skew 50 ps
Duty Cycle
1,3
45 55 %
Output Enable Time
5
All outputs 50 100 ns
Output Disable Time
5
All outputs 50 100 ns
Stabilization Time t
STABLE
From power-up VDD=3.3 V 1.8 ms
Spread Spectrum Transition
Time
t
SPREAD
Stabilization time after spread
spectrum changes
730ms
Parameter Symbol Conditions Min Typ Max Units Notes
Jitter, Phase
t
jphasePLL
PCIe Gen1 32 86 ps (p-p) 1,2,3
t
jphaseLO
PCIe Gen2, 10 kHz < f < 1.5 MHz 0.8 3 ps (RMS) 1,2,3
t
jphaseHIGH
PCIe Gen2, 1.5 MHz < f < Nyquist (50 MHz) 2.3 3.1 ps (RMS) 1,2,3
