OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

NB4N507ADR2G

P1-P3P4-P6P7-P8
© Semiconductor Components Industries, LLC, 2007
September, 2007 - Rev. 3
1 Publication Order Number:
NB4N507A/D
NB4N507A
3.3V/5V, 50 MHz to 200 MHz
PECL Clock Synthesizer
Description
The NB4N507A is a precision clock synthesizer which generates a
very low jitter differential PECL output clock. It produces a clock
output based on an integer multiple of an input reference frequency.
The NB4N507A accepts a standard fundamental mode crystal,
using Phase-Locked-Loop (PLL) techniques, will produce output
clocks up to 200 MHz. In addition, the PLL circuitry will produce a
50% duty cycle square-wave clock output (see Figure 7).
The NB4N507A can be programmed to generate a selection of input
reference frequency multiples. An exact 155.52 MHz output clock can
be generated from a 19.44 MHz crystal and the x8 multiplier selection.
The NB4N507A is intended for low output jitter clock generation.
The PECL outputs are 15 mA open collector and must be DC loaded
and AC terminated. See Figures 4 and 6.
Features
•Input Crystal Frequency of 10 - 27 MHz
•Enable Usage of Common Low-Cost Crystal
•Differential PECL Output Clock Frequencies up to 200 MHz
•Duty Cycle of 48%/52%
•Operating Range: V
CC
= 3.0 V to 5.5 V
•Ideal for SONET Applications and Oscillator Manufacturers
•Available in Die Form
•Packaged in 16-Pin Narrow SOIC
•Pb-Free Packages are Available*
Figure 1. Simplified Logic Block Diagram
Osc
PD
CP
VCO
PECL
Mult
S1S0
CLKOUT
CLKOUT
OE
*For additional information on our Pb-Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
SOIC-16
D SUFFIX
CASE 751B
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
ORDERING INFORMATION
MARKING DIAGRAM
http://onsemi.com
NB4N507AG
AWLYWW
A = Assembly Location
WL = Wafer Lot
Y = Year
WW = Work Week
G = Pb-Free Package
NB4N507A
http://onsemi.com
2
Figure 2. NB4N507A Logic Diagram
Crystal
V
DD
Feedback
Oscillator
Buffer
X1/CLK
X2
Phase
Detector
GND
Charge
Pump
VCO
PECL
Output
Multiplier
Select
S1S0
CLKOUT
CLKOUT
OE
X2
NC
S0
OE
NC
NC
NCNC
GND
GND
S1
V
DD
V
DD
X1/CLK
Figure 3. 16-Pin SOIC (Top View)
16
15
14
13
12
11
10
CLKOUTCLKOUT 9
1
2
3
4
5
6
7
8
Table 1. CLOCK MULTIPLIER SELECT TABLE
S1 S0 Multiplier
L L 9.72X*
L M 10X
L H 12X
M L 6.25X
M M 8X
M H 5X
H L NA
H M 3X
H H 4X
*Example Crystal = 16 MHz, f
CLKOUT
= 155.52 MHz
L = GND
H = V
DD
M = OPEN
Table 2. OE, OUTPUT ENABLE FUNCTION
OE Function
0 Disable
1 Enable
NB4N507A
http://onsemi.com
3
Table 3. PIN DESCRIPTION
Pin #
SOIC-16
Name I/O Description
1 X1/CLK Crystal Input Crystal or Clock Input
2,3 V
DD
Power Supply Positive Supply Voltage (3.0 V to 5.5 V)
4 S1 Tri-Level Input Multiplier Select Pin; When Left Open, Defaults to V
DD
B 2
5,6 GND Power Supply Negative Supply Voltage
7,10,11,12,
15
NC No Connect Pin 10 does not require an external resistor. The NB4N507A will function with or
without a resistor on Pin 10.
8 CLKOUT PECL Output* Non-inverted differential PECL clock output.
9 CLKOUT PECL Output* Inverted differential PECL clock output.
13 OE (LV)CMOS/(LV)TTL
Input
Output Enable for the CLKOUT/CLKOUT Outputs. Outputs are
enabled when HIGH or when left open; OE pin has internal pullup resistor. Disables
both outputs when LOW. CLKOUT goes LOW, CLKOUT goes HIGH.
14 S0 Tri-Level Input Multiplier Select Pin; When Left Open, Defaults to V
DD
B 2
16 X2 Crystal Input Crystal Input
*The PECL Outputs are 15 mA open collector and must be DC loaded and AC terminated. See Figures 4, 5 and 6.
Table 4. ATTRIBUTES
Characteristics Value
ESD Protection Human Body Model
Machine Model
Charged Device Model
> 1 kV
> 150 V
> 1 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Level 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V-0 @ 0.125 in
Transistor Count 1145 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 5. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
V
CC
Positive Power Supply GND = 0 V 6 V
V
I
Input Voltage GND - 0.5 ≤ V
I
≤ V
DD
+ 0.5 V
T
A
Operating Temperature Range -40 to +85 °C
T
stg
Storage Temperature Range -65 to +150 °C
q
JA
Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
SOIC-16 100
60
°C/W
°C/W
q
JC
Thermal Resistance (Junction-to-Case) (Note 2) SOIC-16 33 to 36 °C/W
T
sol
Wave Solder Pb
Pb-Free
< 3 sec @ 248°C
< 3 sec @ 260°C
265
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. JEDEC standard multilayer board - 2S2P (2 signal, 2 power).
P1-P3P4-P6P7-P8

NB4N507ADR2G

Mfr. #:
Buy NB4N507ADR2G
Manufacturer:
ON Semiconductor
Description:
Phase Locked Loops - PLL 3.3V/5V PECL Clock Synthesizer
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet