Document Number: 002-08308 Rev. *C Page 5 of 24
5. Handling Devices
Preventing Latch-up
A latch-up can occur if, on this device, (a) a voltage higher than VDD or a voltage lower than VSS is applied to an input or output pin or
(b) a voltage higher than the rating is applied between V
DD and VSS pins. The latch-up, if it occurs, significantly increases the power
supply current and may cause thermal destruction of an element. When you use this device, be very careful not to exceed the max-
imum rating.
Handling Unused Pins
■ Do not leave an unused input pin open, since it may cause a malfunction. Handle by, using a pull-up or
pull-down resistor.
■ Unused output pin should be opened.
The Attention when the External Clock is Used
■ Input the clock to XIN pin, and XOUT pin should be opened when you use the external clock.
■ Please pay attention so that an overshoot and an undershoot do not occur to an input clock of XIN pin.
Power Supply Pins
■ Please design connecting the power supply pin of this device by as low impedance as possible from the current supply source.
■ We recommend connecting electrolytic capacitor (about 10 μF) and the ceramic capacitor (about 0.01 μF) in parallel between VSS
and V
DD pins near the device, as a bypass capacitor.
Oscillation Circuit
■ Noise near the XIN and XOUT pins may cause the device to malfunction. Design printed circuit boards so that electric wiring of XIN
or XOUT pin and resonator (or ceramic oscillator) do not intersect other wiring.
■ Design the printed circuit board that surrounds the XIN and XOUT pins with ground.
