Document Number: 002-08308 Rev. *C Page 17 of 24
16. Lock-up Time
If the setting pin is fixed at the “H” or “L” level, the maximum time after the power is turned on until the set clock signal is output from
CKOUT pin is (the stabilization wait time of input clock to XIN pin)
+ (the lock-up time “tLK”). For the input clock stabilization time,
check the characteristics of the resonator or oscillator used.
For modulation enable control using the XENS pin during normal operation, the set clock signal is output from
CKOUT pin at most the lock-up time (t
LK) after the level at the XENS pin is determined.
Note: When the pin setting is changed, the CKOUT pin output clock stabilization time is required. Until the output clock signal becomes
stable, the output frequency, output clock duty cycle, modulation period, and cycle-cycle jitter cannot be guaranteed. It is therefore
advisable to perform processing such as cancelling a reset of the device at the succeeding stage after the lock-up time.
3.0 V
VDD
XIN
Setting pin
SEL
FREQ1/XENS
FREQ0/FREQ
V
IH
CKOUT
Internal clock
stabilization wait time
t
LK
(lock-up time )
tLK
(lock-up time )
tLK
(lock-up time )
