74HC_HCT4053_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 22 November 2012 3 of 30
NXP Semiconductors
74HC4053-Q100; 74HCT4053-Q100
Triple 2-channel analog multiplexer/demultiplexer
5. Functional diagram
Fig 1. Functional diagram
001aak341
LOGIC
LEVEL
CONVERSION
11
16
V
CC
13 1Y1
S1
LOGIC
LEVEL
CONVERSION
DECODER
LOGIC
LEVEL
CONVERSION
12 1Y0
14 1Z
1 2Y1
2 2Y0
15 2Z
3 3Y1
5 3Y0
43Z
10
S2
9
87
V
EE
GND
S3
6
E
Fig 2. Logic symbol Fig 3. IEC logic symbol
001aae125
1Y0 12
1Y1
S1
13
11
S210
S39
6
E
2Y0 2
2Y1
1
3Y0 5
3Y1
3
3Z
4
2Z
15
1Z
14
001aae126
6
EN
11
#
#
#
MUX/DMUX
12
13
×
0
1
0/1
0
1
14
10 2
1
15
9 5
3
4
74HC_HCT4053_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 22 November 2012 4 of 30
NXP Semiconductors
74HC4053-Q100; 74HCT4053-Q100
Triple 2-channel analog multiplexer/demultiplexer
6. Pinning information
6.1 Pinning
Fig 4. Schematic diagram (one switch)
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to VCC.
Fig 5. Pin configuration SO16 and TSSOP16 Fig 6. Pin configuration DHVQFN16
74HC4053-Q100
74HCT4053-Q100
2Y1 V
CC
2Y0 2Z
3Y1 1Z
3Z 1Y1
3Y0 1Y0
ES1
V
EE
S2
GND S3
aaa-003164
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
aaa-003165
V
EE
S2
ES1
3Y0 1Y0
3Z 1Y1
3Y1 1Z
2Y0 2Z
GND
S3
2Y1
V
CC
Transparent top view
7 10
6 11
5 12
4
13
3 14
2 15
8
9
1
16
terminal 1
index area
V
CC
(1)
74HC4053-Q100
74HCT4053-Q100
74HC_HCT4053_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 22 November 2012 5 of 30
NXP Semiconductors
74HC4053-Q100; 74HCT4053-Q100
Triple 2-channel analog multiplexer/demultiplexer
6.2 Pin description
7. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.
8. Limiting values
[1] To avoid drawing V
CC
current out of terminal nZ, when switch current flows into terminals nYn, the voltage drop across the bidirectional
switch must not exceed 0.4 V. If the switch current flows into terminal nZ, no V
CC
current flows out of terminals nYn. In this case, there is
no limit for the voltage drop across the switch, but the voltages at nYn and nZ may not exceed V
CC
or V
EE
.
[2] For SO16 package: above 70 C the value of P
tot
derates linearly with 8 mW/K.
For TSSOP16 package: above 60 C the value of P
tot
derates linearly with 5.5 mW/K.
For DHVQFN16 package: above 60 C the value of P
tot
derates linearly with 4.5 mW/K.
Table 2. Pin description
Symbol Pin Description
E
6 enable input (active LOW)
V
EE
7 supply voltage
GND 8 ground supply voltage
S1, S2, S3 11, 10, 9 select input
1Y0, 2Y0, 3Y0 12, 2, 5 independent input or output
1Y1, 2Y1, 3Y1 13, 1, 3 independent input or output
1Z, 2Z, 3Z 14, 15, 4 common output or input
V
CC
16 supply voltage
Table 3. Function table
[1]
Inputs Channel on
E Sn
LLnY0 to nZ
L H nY1 to nZ
H X switches off
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to V
SS
= 0 V (ground).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage
[1]
0.5 +11.0 V
I
IK
input clamping current V
I
< 0.5 V or V
I
>V
CC
+0.5V - 20 mA
I
SK
switch clamping current V
SW
< 0.5 V or V
SW
>V
CC
+0.5V - 20 mA
I
SW
switch current 0.5 V < V
SW
<V
CC
+0.5V - 25 mA
I
EE
supply current - 20 mA
I
CC
supply current - 50 mA
I
GND
ground current - 50 mA
T
stg
storage temperature 65 +150 C
P
tot
total power dissipation
[2]
- 500 mW
P power dissipation per switch - 100 mW

74HCT4053D-Q100,11

Mfr. #:
Manufacturer:
Nexperia
Description:
Multiplexer Switch ICs 74HCT4053D-Q100/SO16/REEL 13
Lifecycle:
New from this manufacturer.
Delivery:
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