13
LT1794
Similar results can be obtained with the LT1794CSW in the
wide SO-20 package. With this package heat is conducted
primarily through the V
–
pins, Pins 4 to 7 and 14 to 17;
these pins should be soldered directly to the PCB metal
plane.
Important Note: The metal planes used for heat sinking
the LT1794 are electrically connected to the negative
supply potential of the driver, typically –12V. These
planes must be isolated from any other power planes
used in the board design.
When PCB cards containing multiple ports are inserted
into a rack in an enclosed cabinet, it is often necessary to
provide airflow through the cabinet and over the cards.
This is also very effective in reducing the junction-to-
ambient thermal resistance of each line driver. To a limit,
this thermal resistance can be reduced approximately
5°C/W for every 100lfpm of laminar airflow.
Layout and Passive Components
With a gain bandwidth product of 200MHz the LT1794
requires attention to detail in order to extract maximum
performance. Use a ground plane, short lead lengths and
a combination of RF-quality supply bypass capacitors (i.e.,
0.1µF). As the primary applications have high drive cur-
rent, use low ESR supply bypass capacitors (1µF to 10µF).
The parallel combination of the feedback resistor and gain
setting resistor on the inverting input can combine with the
input capacitance to form a pole that can cause frequency
peaking. In general, use feedback resistors of 1k or less.
Compensation
The LT1794 is stable in a gain 10 or higher for any supply
and resistive load. It is easily compensated for lower gains
with a single resistor or a resistor plus a capacitor.
Figure␣ 9 shows that for inverting gains, a resistor from the
inverting node to AC ground guarantees stability if the
parallel combination of R
C
and R
G
is less than or equal to
R
F
/9. For lowest distortion and DC output offset, a series
capacitor, C
C
, can be used to reduce the noise gain at
lower frequencies. The break frequency produced by R
C
and C
C
should be less than 5MHz to minimize peaking.
Figure 10 shows compensation in the noninverting con-
figuration. The R
C
, C
C
network acts similarly to the invert-
ing case. The input impedance is not reduced because the
network is bootstrapped. This network can also be placed
between the inverting input and an AC ground.
Another compensation scheme for noninverting circuits is
shown in Figure 11. The circuit is unity gain at low
frequency and a gain of 1 + R
F
/R
G
at high frequency. The
DC output offset is reduced by a factor of ten. The
techniques of Figures 10 and 11 can be combined as
shown in Figure 12. The gain is unity at low frequencies,
1 + R
F
/R
G
at mid-band and for stability, a gain of 10 or
greater at high frequencies.
Figure 9. Compensation for Inverting Gains
APPLICATIO S I FOR ATIO
WUUU
R
G
R
C
V
O
V
I
C
C
(OPTIONAL)
–
+
1794 F09
R
F
=
–R
F
R
G
V
O
V
I
< 5MHz
1
2πR
C
C
C
(R
C
|| R
G
) ≤ R
F
/9
R
C
V
O
V
I
C
C
(OPTIONAL)
+
–
1794 F10
R
F
R
G
= 1 +
R
F
R
G
V
O
V
I
< 5MHz
1
2πR
C
C
C
(R
C
|| R
G
) ≤ R
F
/9
Figure 10. Compensation for Noninverting Gains
+
–
1794 F11
R
F
R
G
V
i
V
O
C
C
< 5MHz
1
2πR
G
C
C
R
G
≤ R
F
/9
= 1 (LOW FREQUENCIES)
(HIGH FREQUENCIES)
V
O
V
I
= 1 +
R
F
R
G
Figure 11. Alternate Noninverting Compensation
