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LT1794IFE#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
7
LT1794
9
2
8
–12V
1k
12V
3
19
10 (SHDN)
R
SHDN
4
5
6
7
110Ω
OUT (+)
OUT (–)
10k
E
IN
0.01µF
R
L
≈ 50Ω
1:2*
10k
49.9Ω
110Ω
12.7Ω
1794 TC
14
15
16
17
18
11 (SHDNREF)
–
+
A
13
12
1k
0.1µF 4.7µF
0.1µF
12V
–12V
–
+
B
–12V
12.7Ω
V
OUT(P-P)
100 LINE LOAD
SUPPLY BYPASSING
*COILCRAFT X8390-A OR EQUIVALENT
V
OUTP-P
AMPLITUDE SET AT EACH AMPLIFIER OUTPUT
DISTORTION MEASURED ACROSS LINE LOAD
SPLITTER
MINICIRCUITS
ZSC5-2-2
+
+
4.7µF
+
0.1µF
4.7µF
TEST CIRCUIT
APPLICATIO S I FOR ATIO
WUUU
The LT1794 is a high speed, 200MHz gain bandwidth
product, dual voltage feedback amplifier with high output
current drive capability, 500mA source and sink. The
LT1794 is ideal for use as a line driver in xDSL data
communication applications. The output voltage swing
has been optimized to provide sufficient headroom when
operating from ±12V power supplies in full-rate ADSL
applications. The LT1794 also allows for an adjustment of
the operating current to minimize power consumption. In
addition, the LT1794 is available in small footprint surface
mount packages to minimize PCB area in multiport central
office DSL cards.
To minimize signal distortion, the LT1794 amplifiers are
decompensated to provide very high open-loop gain at
high frequency. As a result each amplifier is frequency
stable with a closed-loop gain of 10 or more. If a closed-
loop gain of less than 10 is desired, external frequency
compensating components can be used.
Setting the Quiescent Operating Current
Power consumption and dissipation are critical concerns
in multiport xDSL applications. Two pins, Shutdown
(SHDN) and Shutdown Reference (SHDNREF), are pro-
vided to control quiescent power consumption and allow
for the complete shutdown of the driver. The quiescent
current should be set high enough to prevent distortion
induced errors in a particular application, but not so high
that power is wasted in the driver unnecessarily. A good
starting point to evaluate the LT1794 is to set the quiescent
current to 10mA per amplifier.
The internal biasing circuitry is shown in Figure 1. Ground-
ing the SHDNREF pin and directly driving the SHDN pin with
a voltage can control the operating current as seen in the
Typical Performance Characteristics. When the SHDN pin
is less than SHDNREF + 0.4V, the driver is shut down and
consumes typically only 100µA of supply current and the
8
LT1794
outputs are in a high impedance state. Part to part varia-
tions however, will cause inconsistent control of the qui-
escent current if direct voltage drive of the SHDN pin is used.
Using a single external resistor, R
BIAS
, connected in one of
two ways provides a much more predictable control of the
quiescent supply current. Figure 2 illustrates the effect on
supply current per amplifier with R
BIAS
connected be-
tween the SHDN pin and the 12V V
+
supply of the LT1794
and the approximate design equations. Figure 3 illustrates
the same control with R
BIAS
connected between the
SHDNREF pin and ground while the SHDN pin is tied to V
+
.
Either approach is equally effective.
APPLICATIO S I FOR ATIO
WUUU
Figure 1. Internal Current Biasing Circuitry
2k
SHDN
SHDNREF
TO
START-UP
CIRCUITRY
1k
1794 F01
I
BIAS
TO AMPLIFIERS
BIAS CIRCUITRY
2I
I
2I
5I
2
5
I
BIAS
=
I
SUPPLY
PER AMPLIFIER (mA) = 64 • I
BIAS
I
SHDN
= I
SHDNREF
R
BIAS
(kΩ)
0
I
SUPPLY
PER AMPLIFIER (mA)
10
20
30
5
15
25
10
1794 F02
7 40 70 100 130 160 190
V
S
= ±12V
V
+
= 12V
R
BIAS
SHDN
SHDNREF
R
BIAS
=
• 25.6 – 2k
V
+
– 1.2V
I
S
PER AMPLIFIER (mA)
I
S
PER AMPLIFIER
(mA)
• 25.6
V
+
– 1.2V
R
BIAS
+ 2k
≈
R
BIAS
(kΩ)
4 7 10 50 90 130 170 210 25030 70 100 150 190 230 270 290
I
SUPPLY
PER AMPLIFIER (mA)
20
25
30
35
40
1794 F03
5
10
15
0
45
V
S
= ±12V
V
+
= 12V
R
BIAS
SHDN
SHDNREF
R
BIAS
=
• 64 – 5k
V
+
– 1.2V
I
S
PER AMPLIFIER (mA)
I
S
PER AMPLIFIER
(mA)
• 64
V
+
– 1.2V
R
BIAS
+ 5k
≈
Figure 2. R
BIAS
to V
+
Current Control
Figure 3. R
BIAS
to Ground Current Control
9
LT1794
Two Control Inputs
RESISTOR VALUES (kΩ)
R
SHDN
TO V
CC
(12V) R
SHDN
TO V
LOGIC
V
LOGIC
R
SHDN
R
C1
R
CO
3V
40.2
11.5
19.1
3.3V
43.2
13.0
22.1
5V
60.4
21.5
36.5
3V
4.99
8.66
14.3
3.3V
6.81
10.7
17.8
5V
19.6
20.5
34.0
V
C0
H
L
H
L
V
C1
H
H
L
L
10
7
5
2
10
7
5
2
10
7
5
2
10
7
5
2
10
7
5
2
10
7
5
2
SUPPLY CURRENT PER AMPLIFIER (mA)
One Control Input
RESISTOR VALUES (kΩ)
R
SHDN
TO V
CC
(12V) R
SHDN
TO V
LOGIC
V
LOGIC
R
SHDN
R
C
3V
40.2
7.32
3.3V
43.2
8.25
5V
60.4
13.7
3V
4.99
5.49
3.3V
6.81
6.65
5V
19.6
12.7
V
C
H
L
10
2
10
2
10
2
10
2
10
2
10
2
SUPPLY CURRENT PER AMPLIFIER (mA)
R
SHDN
R
C1
V
C1
V
LOGIC
12V OR V
LOGIC
0V
V
C0
R
C0
SHDN
SHDNREF
2k
R
SHDN
R
C
V
C
V
LOGIC
12V OR V
LOGIC
0V
SHDN
SHDNREF
1794 F04
2k
APPLICATIO S I FOR ATIO
WUUU
Logic Controlled Operating Current
The DSP controller in a typical xDSL application can have
I/O pins assigned to provide logic control of the LT1794
line driver operating current. As shown in Figure 4 one or
two logic control inputs can control two or four different
operating modes. The logic inputs add or subtract current
to the SHDN input to set the operating current. The one
logic input example selects the supply current to be either
full power, 10mA per amplifier or just 2mA per amplifier,
which significantly reduces the driver power consumption
while maintaining less than 2Ω output impedance to
frequencies less than 1MHz. This low power mode retains
termination impedance at the amplifier outputs and the
line driving back termination resistors. With this termina-
tion, while a DSL port is not transmitting data, it can still
sense a received signal from the line across the back-
termination resistors and respond accordingly.
The two logic input control provides two intermediate
(approximately 7mA per amplifier and 5mA per amplifier)
operating levels between full power and termination modes.
These modes can be useful for overall system power
management when full power transmissions are not
necessary.
Shutdown and Recovery
The ultimate power saving action on a completely idle port
is to fully shut down the line driver by pulling the SHDN pin
to within 0.4V of the SHDNREF potential. As shown in
Figure 5 complete shutdown occurs in less than 10µs and,
more importantly, complete recovery from the shut down
state to full operation occurs in less than 2µs. The biasing
circuitry in the LT1794 reacts very quickly to bring the
amplifiers back to normal operation.
Figure 4. Providing Logic Input Control of Operating Current
V
SHDN
SHDNREF = 0V
AMPLIFIER
OUTPUT
1794 F05
Figure 5. Shutdown and Recovery Timing
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

LT1794IFE#PBF

Mfr. #:
Buy LT1794IFE#PBF
Manufacturer:
Analog Devices Inc.
Description:
High Speed Operational Amplifiers 2x 500mA, 200MHz xDSL Line Drvr Amp
Lifecycle:
New from this manufacturer.
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