19©2017 Integrated Device Technology, Inc. December 1, 2017
9ZML1233E / 9ZML1253E Datasheet
SMBus Table: Device ID
SMBus Table: Byte Count Register
SMBus Table: Output Skew Register A (when Input Clock A is selected)
Note: For example, at 2.4GHz, each VCO period is 416.7ps and there are 24 VCO periods in a 100MHz output. Each write to bits [2:0] will
pull the output a early by that number of VCO periods. Writing “110” 4 times would pull the output back in phase with the input. Writing
“001” twice will accomplish the same result as writing “010” once - pulling the output 2 VCO periods earlier.
Byte 6 Name Control Function Type 0 1 Default
Bit 7 Device ID 7 (MSB) R
9ZML1233=ED
9ZML1253=FD
1
Bit 6 Device ID 6 R 1
Bit 5 Device ID 5 R 1
Bit 4 Device ID 4 R X
Bit 3 Device ID 3 R 1
Bit 2 Device ID 2 R 1
Bit 1 Device ID 1 R 0
Bit 0 Device ID 0 R X
Byte 7 Name Control Function Type 0 1 Default
Bit 7
Reserved 0
Bit 6 Reserved 0
Bit 5 Reserved 0
Bit 4 BC4
Writing to this register configures how
many bytes will be read back.
RW
Default value is 8 hex, so 9 bytes (0 to
8) will be read back by default.
0
Bit 3 BC3 RW 1
Bit 2 BC2 RW 0
Bit 1 BC1 RW 0
Bit 0 BC0 RW 0
Byte 8 Name Control Function Type 0 1 Default
Bit 7
Reserved 0
Bit 6 Reserved 0
Bit 5
Reserved 0
Bit 4 Reserved 0
Bit 3 Reserved 0
Bit 2 I2O_FB_ASkew2
Channel A Output delay programming
(early)
RW
Binary value of number of VCO periods
that outputs will be pulled earlier than
input.
0
Bit 1 I2O_FB_ASkew1 RW 0
Bit 0 I2O_FB_ASkew0 RW 0
