7©2017 Integrated Device Technology, Inc. December 1, 2017
9ZML1233E / 9ZML1253E Datasheet
1
Guaranteed by design and characterization, not 100% tested in production.
2
Control input must be monotonic from 20% to 80% of input swing.
3
Time from deassertion until outputs are > 200mV, PLL Mode.
4
DIF_IN input.
5
This parameter reflects the operating range after locking to a 100MHz input.
Table 5. Input/Supply/Common Parameters
Parameter Symbol Conditions Minimum Typical Maximum Units Notes
Supply Voltage
V
DD
x Supply voltage for core and analog. 3.135 3.3 3.465 V
V
DDIO
Supply voltage for differential outputs. 3.135 3.3 3.465 V
Ambient Operating
Temperature
T
AMB
Industrial range. -40 85 °C
Input High Voltage V
IH
Single-ended inputs, except SMBus, tri-level
inputs.
2V
DD
+ 0.3 V
Input Low Voltage V
IL
Single-ended inputs, except SMBus, tri-level
inputs.
GND
- 0.3 0.8 V
Input High Voltage V
IH
Tri-level inputs (“_tri” suffix). 2.2 V
DD
+ 0.3 V
Input Mid Voltage V
IM
Tri-level inputs (“_tri” suffix). 1.2 V
DD
/2 1.8 V
Input Low Voltage V
IL
Tri-level inputs (“_tri” suffix). GND
- 0.3 0.8 V
Input Current
I
IN
Single-ended inputs, V
IN
= GND, V
IN
= V
DDx.
-5 5 μA
I
INP
Single-ended inputs
V
IN
= 0 V; Inputs with internal pull-up resistors.
V
IN
= V
DD;
Inputs with internal pull-down
resistors.
-100 100 μA
Input Frequency
F
IBYP
V
DD
= 3.3V, Bypass Mode. 1 400 MHz
F
IPLL
V
DD
= 3.3V, 100MHz PLL Mode. 98.5 100.00 102 MHz 5
Pin Inductance L
pin
7nH1
Capacitance
C
IN
Logic Inputs, except DIF_IN. 1.5 5 pF 1
C
INDIF_IN
DIF_IN differential clock inputs. 1.5 2.7 pF 1,4
C
OUT
Output pin capacitance. 6 pF 1
Clk Stabilization t
STAB
From V
DD
power-up and after input clock
stabilization or deassertion of PD# to 1st clock.
1.2 1.8 ms 1,2
Input SS
Modulation
Frequency PCIe
f
MODINPCIe
Allowable frequency for PCIe applications
(triangular modulation).
30 31.6 33 kHz
OE# Latency t
LATOE#
DIF start after OE# assertion.
DIF stop after OE# deassertion.
4 5 10 clocks 1,2,3
Tdrive_PD# t
DRVPD
DIF output enable after PD# deassertion. 85 300 μs1,3
Tfall t
F
Fall time of control inputs. 5 ns 2
Trise t
R
Rise time of control inputs. 5 ns 2
8©2017 Integrated Device Technology, Inc. December 1, 2017
9ZML1233E / 9ZML1253E Datasheet
1
Includes V
DDR
if applicable.
Table 6. Current Consumption
Parameter Symbol Conditions Minimum Typical Maximum Units Notes
Operating Supply
Current
I
DDx
All other V
DD
pins, all outputs at 100MHz,
C
L
= 2pF; Zo = 85.
22 30 mA
I
DDA+R
V
DDA
+ V
DDR
pins, all outputs at 100MHz,
C
L
= 2pF; Zo = 85.
56 65 mA 1
I
DDO
V
DDIO
pins, all outputs at 100MHz, C
L
= 2pF;
Zo = 85.
84 100 mA
Power Down
Current
I
DDx
All other V
DD
pins, all outputs Low/Low. 0.9 2 mA 1
I
DDA+R
V
DDA
+ V
DDR
pins, all outputs Low/Low. 4.3 6 mA 1
I
DDO
V
DDIO
pins, all outputs Low/Low. 0.1 0.2 mA 1
Table 7. Skew and Differential Jitter Parameters
Parameter Symbol Conditions Minimum Typical Maximum Units Notes
CLK_IN, DIF[x:0] t
SKEW_PLL
Input-to-output skew in PLL Mode at 100MHz,
nominal temperature and voltage.
-100 -4 100 ps
1,2,4,
5,6,8
CLK_IN, DIF[x:0] t
PD_BYP
Input-to-output skew in Bypass Mode at
100MHz, nominal temperature and voltage.
2.2 2.9 3.6 ns
1,2,3,
8
CLK_IN, DIF[x:0] t
DSPO_PLL
Input-to-output skew variation in PLL Mode at
100MHz, across voltage and temperature.
-50 0.0 50 ps
1,2,3,
8
CLK_IN, DIF[x:0] t
DSPO_BYP
Input-to-output skew variation in Bypass Mode
at 100MHz, across voltage and temperature,
T
AMB
= 0 to 70°C, default slew rate.
-250 0.0 250 ps
1,2,3,
8
Input-to-output skew variation in Bypass Mode
at 100MHz, across voltage and temperature,
T
AMB
= -40 to 85°C, default slew rate.
-350 0.0 350 ps
1,2,3,
8
DIF[x:0] t
SKEW_ALL
Output-to-output skew across all outputs,
common to PLL and Bypass Mode, at 100MHz,
default slew rate.
30 50 ps
1,2,3,
8
PLL Jitter Peaking j
peak-hibw
LOBW#_BYPASS_HIBW = 1. 0 1.3 2.5 dB 7,8
PLL Jitter Peaking j
peak-lobw
LOBW#_BYPASS_HIBW = 0. 0 1.3 2 dB 7,8
PLL Bandwidth pll
HIBW
LOBW#_BYPASS_HIBW = 1. 2 2.6 4 MHz 8,9
PLL Bandwidth pll
LOBW
LOBW#_BYPASS_HIBW = 0. 0.7 1.0 1.4 MHz 8,9
Duty Cycle t
DC
Measured differentially, PLL Mode. 45 50 55 % 1
Duty Cycle
Distortion
t
DCD
Measured differentially, Bypass Mode at
100MHz.
-1 -0.2 0 % 1,10
Jitter, Cycle to Cycle t
jcyc-cyc
PLL Mode. 13 50 ps 1,11
Additive jitter in Bypass Mode. 0.2 5 ps 1,11
9©2017 Integrated Device Technology, Inc. December 1, 2017
9ZML1233E / 9ZML1253E Datasheet
1
Measured into fixed 2pF load cap. Input to output skew is measured at the first output edge following the corresponding input.
2
Measured from differential cross-point to differential cross-point. This parameter can be tuned with external feedback path, if present.
3
All Bypass Mode input-to-output specs refer to the timing between an input edge and the specific output edge created by it.
4
This parameter is deterministic for a given device.
5
Measured with scope averaging on to find mean value.
6
This value is programmable.
7
Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking.
8
Guaranteed by design and characterization, not 100% tested in production.
9
Measured at 3db down or half power point.
10
Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in Bypass
Mode.
11
Measured from differential waveform.
1
Guaranteed by design and characterization, not 100% tested in production.
2
Measured from differential waveform.
3
Slew rate is measured through the V
SWING
voltage range centered around differential 0 V. This results in a ±150mV window around
differential 0V.
4
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a ±75mV window centered on the
average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5
V
CROSS
is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
6
The total variation of all V
CROSS
measurements in any particular system. Note that this is a subset of V
CROSS_MIN/MAX
(V
CROSS
absolute) allowed. The intent is to limit V
CROSS
induced modulation by setting Δ-V
CROSS
to be smaller than V
CROSS
absolute.
7
At default SMBus settings.
8
If driving a receiver with input terminations, the V
MAX
and V
MIN
values will be halved.
Table 8. DIF HCSL/LP-HCSL Outputs
Parameter Symbol Conditions Minimum Typical Maximum
Industry
Limits
Units Notes
Slew Rate dV/dt Scope averaging on. 2.0 2.8 4.0 0.6 – 4.0 V/ns 1,2,3
Slew Rate Matching ΔdV/dt
Slew rate matching, scope
averaging on.
415 20%
1,2,4,
7
Maximum Voltage V
MAX
Measurement on
single-ended signal using
absolute value (scope
averaging off).
660 794 870 1150
mV
7,8
Minimum Voltage V
MIN
-111 -49 -300 7,8
Crossing Voltage (abs) V
CROSS_ABS
Scope averaging off. 302 367 453 250 – 550 mV 1,5,7
Crossing Voltage (var) Δ-V
CROSS
Scope averaging off. 32 74 140 mV 1,6,7

9ZML1253EKILF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer DB1200ZL OEM MUX DERIV "LITE" + WRTLK
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