MP5002DQ-LF-P

MP5002 – 3.3V, 1A-3A PROGRAMMABLE CURRENT LIMIT SWITCH
MP5002 Rev. 0.93 www.MonolithicPower.com 10
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© 2010 MPS. All Rights Reserved.
The fault flag is an internal flip-flop that can be
set or reset under various conditions:
1. Thermal Shutdown: set fault flag
2. Under Voltage: reset fault flag
3. Low voltage on Enable/Fault pin: reset
fault flag
4. Mid voltage on Enable/Fault pin: no
effect
5. Under a fault, the Enable/Fault pin is
driven to the mid level.
There are 4 types of faults, and each fault has a
direct and indirect effect on the Enable/Fault pin
and the internal fault flag. In a typical application
where there are multiple MP5002 chips in a
system, the enable/fault lines are typically
connected together.
Table 3—Fault Function Influence in Application
Fault description Internal action
Effect on Fault
Pin
Effect on
Flag
Effect on secondary
Part
Short/over current Limit current none none none
Under Voltage Output is turned off
Internally drives
Enable/Fault pin to
Logic low
Flag is
reset
Secondary part output is
disabled, and fault flag is
reset.
Over Voltage Limit output voltage None None None
Thermal Shutdown
Shutdown part. The
part is latched off
until a UVLO or
externally driven to
ground.
Internally drives
Enable/Fault pin
to mid level
Flag is Set
Secondary part output is
disabled.
UNDER VOLTAGE LOCK OUT OPERATION
If the supply (input) is below the UVLO threshold,
the output is disabled, and the fault line is driven
low. When the supply goes above the UVLO
threshold, the output is enabled and the fault line
is released. When the fault line is released it will
be pulled high by a 25uA current V
OUT
. No
external pull up resistor is required. In addition,
the pull up voltage is limited to 5 volts.
THERMAL PROTECTION
When thermal protection is triggered, the output
is disabled and the fault line is driven to the mid
level. The thermal fault condition is latched
(meaning the fault flag is set), and the part will
remain latched off until the fault (enable) line is
brought low. Cycling the power below the UVLO
threshold will also reset the fault flag.
MP5002 – 3.3V, 1A-3A PROGRAMMABLE CURRENT LIMIT SWITCH
MP5002 Rev. 0.93 www.MonolithicPower.com 11
10/15/2010 MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2010 MPS. All Rights Reserved.
PCB LAYOUT
PCB layout is very important to achieve stable
operation. Please follow these guidelines and
take below figure for reference.
Place Rlimit close to Ilimit pin, Cdv/dt close to
dv/dt pin and input cap close to VIN (Exposed
Pad). Keep the N/C pin float. Put vias in thermal
pad and ensure enough copper area near VIN
and VOUT to achieve better thermal
performance.
C2
C4
R
LIMIT Cdv/dt
Top Layer Bottom Layer
Figure 3—PCB Layout
MP5002 – 3.3V, 1A-3A PROGRAMMABLE CURRENT LIMIT SWITCH
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
MP5002 Rev. 0.93 www.MonolithicPower.com 12
10/15/2010 MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2010 MPS. All Rights Reserved.
PACKAGE INFORMATION
QFN10 (3mm x 3mm)
SIDE VIEW
TOP VIEW
110
6
5
BOTTOM VIEW
2.90
3.10
1.45
1.75
2.90
3.10
2.25
2.55
0.50
BSC
0.18
0.30
0.80
1.00
0.00
0.05
0.20 REF
PIN 1 ID
MARKING
1.70
0.50
0.25
RECOMMENDED LAND PATTERN
2.90
NOTE:
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH.
3) LEAD COPLANARITY SHALL BE 0.10 MILLIMETER MAX.
4) DRAWING CONFORMS TO JEDEC MO-229, VARIATION VEED-5.
5) DRAWING IS NOT TO SCALE.
PIN 1 ID
SEE DETAIL A
2.50
0.70
PIN 1 ID OPTION B
R0.20 TYP.
PIN 1 ID OPTION A
R0.20 TYP.
DETAIL A
0.30
0.50
PIN 1 ID
INDEX AREA

MP5002DQ-LF-P

Mfr. #:
Manufacturer:
Monolithic Power Systems (MPS)
Description:
Power Switch ICs - Power Distribution 3.3V 1-3A Prog Current Limit Switch
Lifecycle:
New from this manufacturer.
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