12
LT1632/LT1633
sn1632 16323fs
APPLICATIONS INFORMATION
WUU
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amplifiers operate over a very wide supply range, it is
possible to exceed the maximum junction temperature of
150°C in plastic packages under certain conditions. Junc-
tion temperature T
J
is calculated from the ambient tem-
perature T
A
and power dissipation P
D
as follows:
LT1632CN8: T
J
= T
A
+ (P
D
• 130°C/W)
LT1632CS8: T
J
= T
A
+ (P
D
• 190°C/W)
LT1633CS: T
J
= T
A
+ (P
D
• 150°C/W)
The power dissipation in the IC is the function of the supply
voltage, output voltage and load resistance. For a given
supply voltage, the worst-case power dissipation P
DMAX
occurs at the maximum supply current and when the
output voltage is at half of either supply voltage (or the
maximum swing if less than 1/2 supply voltage). There-
fore P
DMAX
is given by:
P
DMAX
= (V
S
• I
SMAX
) + (V
S
/2)
2
/R
L
To ensure that the LT1632/LT1633 are used properly,
calculate the worst-case power dissipation, use the ther-
mal resistance for a chosen package and its maximum
junction temperature to derive the maximum ambient
temperature.
Example: An LT1632CS8 operating on ±15V supplies and
driving a 500Ω, the worst-case power dissipation per
amplifier is given by:
P
DMAX
= (30V • 5.6mA) + (15V – 7.5V)(7.5/500)
= 0.168 + 0.113 = 0.281W
If both amplifiers are loaded simultaneously, then the total
power dissipation is 0.562W. The SO-8 package has a
junction-to-ambient thermal resistance of 190°C/W in still
air. Therefore, the maximum ambient temperature that the
part is allowed to operate is:
T
A
= T
J
– (P
DMAX
• 190°C/W)
T
A
= 150°C – (0.562W • 190°C/W) = 43°C
For a higher operating temperature, lower the supply
voltage or use the DIP package part.
Input Offset Voltage
The offset voltage changes depending upon which input
stage is active, and the maximum offset voltages are
trimmed to less than 1350µV. To maintain the precision
characteristics of the amplifier, the change of V
OS
over the
entire input common mode range (CMRR) is guaranteed
to be less than 1500µV on a single 5V supply.
Input Bias Current
The input bias current polarity depends on the input
common mode voltage. When the PNP differential pair is
active, the input bias currents flow out of the input pins.
Q4
Q6
V
BIAS
D7D5
+IN
D2
Q3
Q7
Q1
I
1
I
2
+
+
Q9
Q2
D4
D1
D3
–IN
OUT
V
–
V
+
D8D6
Q5
Q12
Q8
Q14
1632/33 F01
C1
R1
R6
225Ω
R7
225Ω
R3
V
–
C
C
R4 R5
C2
R2
Q11 Q13
Q15
BUFFER
AND
OUTPUT BIAS
Figure 1. LT1632 Simplified Schematic Diagram