ADA4424-6
Rev. C | Page 6 of 16
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
3.3 V Supply Voltage 3.6 V
5 V Supply Voltage 5.5 V
Digital Input Voltage (Pin 2 to Pin 5, Pin 8,
Pin 12, Pin 15, Pin 16, Pin 23)
3.6 V
Power Dissipation See Figure 2
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature (Soldering, 10 sec) 300°C
Junction Temperature 150°C
The power dissipated in the package (P
D
) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (V
S
) times the
quiescent current (I
S
). The power dissipated due to load drive
depends on the particular application. For each output, the
power due to load drive is calculated by multiplying the load
current by the associated voltage drop across the device. The
power dissipated due to the loads is equal to the sum of the
power dissipations due to each individual load. RMS voltages
and currents must be used in these calculations.
Airflow increases heat dissipation, effectively reducing θ
JA
.
Figure 2 shows the maximum power dissipation in the package
vs. the ambient temperature for the 38-lead TSSOP (67.6°C/W)
on a JEDEC standard 4-layer board. θ
JA
values are approximate.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
2.4
0
0 100
AMBIENT TEMPERATURE (°C)
MAXIMUM POWER DISSIPATION (W)
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
10 20 30 40 50 60 70 80 90
08550-002
THERMAL RESISTANCE
θ
JA
is specified for the device soldered to a high thermal
conductivity 4-layer (2s2p) circuit board, as described in
EIA/JESD 51-7.
Table 3.
Package Type θ
JA
θ
JC
Unit
38-Lead TSSOP 67.6 14.0 °C/W
MAXIMUM POWER DISSIPATION
Figure 2. Maximum Power Dissipation vs.
Ambient Temperature for a 4-Layer Board
The maximum safe power dissipation in the ADA4424-6
package is limited by the associated rise in junction temperature
(T
J
) on the die. At approximately 150°C, which is the glass
transition temperature, the plastic changes its properties. Even
temporarily exceeding this temperature limit can change the
stresses that the package exerts on the die, permanently shifting
the parametric performance of the ADA4424-6. Exceeding a
junction temperature of 150°C for an extended time can result
in changes in the silicon devices, potentially causing failure.
ESD CAUTION
ADA4424-6
Rev. C | Page 7 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
D1
D2
D3
VDD3_SD
Y_IN
S
GND5
SD_ENABLE
C_IN
GND3
HPr_IN
FC_SEL
HY_IN
HPb_IN
HD_ENABLE
C1a
OFFSET_ENB
MODE0
VDD3_CP
L1_OUT
L2_OUT
L3_OUT
VSS_SD
Y_OUT
S1/S2_OUT
CVBS_OUT
C_OUT
GND3
HPr_OUT
HPb_OUT
VSS_HD
HY_OUT
VDD3_HD
GND_CP
C1b
C2/CP_OUT
MODE1
VDD5
ADA4424-6
TOP VIEW
(Not to Scale)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19 20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
08550-003
Figure 3. Pin Configuration, Top View
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 GND5 Ground Pin for 5 V Supply.
2 D1 D-Terminal Vertical Resolution Selection Input.
3 D2 D-Terminal Scan Selection Input.
4 D3 D-Terminal Aspect Ratio Selection Input.
5 S S-Terminal Aspect Ratio Selection Input.
6 Y_IN SD Luma (Y) Input.
7 VDD3_SD 3.3 V Supply Pin for SD Filter Section.
8 SD_ENABLE Output Enable Pin for SD (Y, C, CVBS).
9 C_IN SD Chroma (C) Input.
10, 29 GND3 Ground Pins for 3.3 V Supply.
11 HY_IN ED/HD Y Component Input.
12 FC_SEL Filter Corner Frequency Selection Pin for HY, HPb, HPr Channels.
13 HPb_IN ED/HD Pb Component Input.
14 HPr_IN ED/HD Pr Component Input.
15 HD_ENABLE Output Enable Pin for ED/HD (HY, HPb, HPr).
16 MODE0
This pin selects sync tip or back porch sampling when MODE1 = 0 and selects high or low fixed offset
subtraction when MODE1 = 1.
17 OFFSET_ENB Offset Cancellation Enable Pin.
18 VDD3_CP 3.3 V Supply Pins for Charge Pump Section.
19, 21 C1a, C1b Charge Pump Capacitor C1 Connection Pin.
20 GND_CP Ground Pin for 3.3 V Charge Pump Supply.
22 C2/CP_OUT Charge Pump Output Pin. Connect Capacitor C2 from this pin to ground.
23 MODE1 Selects Automatic or Fixed Offset Subtraction Mode.
24 VDD3_HD 3.3 V Supply Pin for ED/HD Filter Section.
25 HPr_OUT ED/HD Pr Component Output.
26 HPb_OUT ED/HD Pb Component Output.
27 VSS_HD
Negative Supply Pin for ED/HD Filter Section. This pin should be connected to the charge pump output
(Pin 22), as shown in Figure 18.
28 HY_OUT ED/HD Y Component Output.
30 C_OUT SD Chroma (C) Output.
31 CVBS_OUT SD Composite Video (CVBS) Output.
ADA4424-6
Rev. C | Page 8 of 16
Pin No. Mnemonic Description
32 VSS_SD
Negative Supply Pin for SD Filter Section. This pin should be connected to the charge pump output (Pin 22), as
shown in Figure 18.
33 Y_OUT SD Luma (Y) Output.
34 S1/S2_OUT S-Terminal Aspect Ratio Selection Output.
35 L3_OUT D-Terminal Aspect Ratio Selection Output.
36 L2_OUT D-Terminal Scan Selection Output.
37 L1_OUT D-Terminal Vertical Resolution Selection Output.
38 VDD5 5 V Supply Pin for D-Terminal and S-Terminal Signaling.

ADA4424-6ARUZ-RL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Video ICs 6 CHl SD/ED/HD Video Filter Charge Pump
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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