10
LT3028
3028f
SHDN1/SHDN2 (Pins 15/10)/(Pins 14/11): Shutdown.
The SHDN1/SHDN2 pins are used to put the correspond-
ing output of the LT3028 regulator into a low power
shutdown state. The output will be off when the pin is
pulled low. The SHDN1/SHDN2 pins can be driven either
by 5V logic or open-collector logic with pull-up resistors.
The pull-up resistors are required to supply the pull-up
current of the open-collector gates, normally several mi-
croamperes, and the SHDN1/SHDN2 pin current, typically
1µA. If unused, the pin must be connected to V
IN
. The
device will not function if the SHDN1/SHDN2 pins are not
connected.
IN1/IN2 (Pins 13, 14/11, 12)/(Pins 13/12): Inputs. Power
is supplied to the device through the IN pins. A bypass
capacitor is required on these pins if the device is more
than six inches away from the main input filter capacitor.
In general, the output impedance of a battery rises with
frequency, so it is advisable to include a bypass capacitor
in battery-powered circuits. A bypass capacitor in the
range of 1µF to 10µF is sufficient. The LT3028 regulator is
designed to withstand reverse voltages on the IN pins with
respect to ground and the OUT pins. In the case of a
reverse input, which can happen if a battery is plugged in
backwards, the device will act as if there is a diode in series
with its input. There will be no reverse current flow into the
regulator and no reverse voltage will appear at the load.
The device will protect both itself and the load.
GND (Pins 5, 17)/(Pins 1, 5, 8, 9, 16, 17): Ground. The
Exposed Pad must be soldered to PCB ground for opti-
mum thermal performance.
ADJ1/ADJ2 (Pins 16/9)/(Pins 15/10): Adjust Pin. These
are the inputs to the error amplifiers. These pins are
internally clamped to ±7V. They have a bias current of
30nA which flows into the pin (see curve of ADJ1/ADJ2 Pin
Bias Current vs Temperature in the Typical Performance
Characteristics section). The ADJ1 and ADJ2 pin voltage
is 1.22V referenced to ground and the output voltage
range is 1.22V to 20V.
BYP1/BYP2 (Pins 1/8)/(Pins 2/7): Bypass. The BYP1/BYP2
pins are used to bypass the reference of the LT3028
regulator to achieve low noise performance from the
regulator. The BYP1/BYP2 pins are clamped internally to
±0.6V (one V
BE
) from ground. A small capacitor from the
corresponding output to this pin will bypass the reference
to lower the output voltage noise. A maximum value of
0.01µF can be used for reducing output voltage noise to a
typical 20µV
RMS
over a 10Hz to 100kHz bandwidth. If not
used, this pin must be left unconnected.
OUT1/OUT2 (Pins 3, 4/6, 7)/(Pins 3, 4/6): Output. The
outputs supply power to the loads. A minimum output
capacitor of 1µF is required to prevent oscillations on
Output 2; Output 1 requires a minimum of 3.3µF. Larger
output capacitors will be required for applications with
large transient loads to limit peak voltage transients. See
the Applications Information section for more information
on output capacitance and reverse output characteristics.
UU
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PI FU CTIO S
(DFN Package)/(TSSOP Package)
APPLICATIO S I FOR ATIO
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The LT3028 is a dual 100mA/500mA low dropout regula-
tor with independent inputs, micropower quiescent cur-
rent, and shutdown. The device is capable of supplying
100mA from Output 2 at a dropout voltage of 300mV.
Output 1 delivers 500mA at a dropout voltage of 320mV.
The two regulators have common GND pins and are
thermally coupled, however, the two inputs and outputs of
the LT3028 operate independently. They can be shut down
independently and a fault condition on one output will not
affect the other output electrically. Output voltage noise
can be lowered to 20µV
RMS
over a 10Hz to 100kHz
bandwidth with the addition of a 0.01µF reference bypass
capacitor. Additionally, the reference bypass capacitor will
improve transient response of the regulator, lowering the
settling time for transient load conditions. The low oper-
ating quiescent current (30µA per output) drops to less
