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9ZXL1231AKLF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
REVISION J 05/25/16 7 12-OUTPUT DB1200ZL
9ZXL1231 DATASHEET
Electrical Characteristics–Input/Supply/Common Output Parameters
T
AMB
= T
COM
or T
IND
, unless noted., Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Supply Voltage VDDx Supply voltage, except VDDIO 3.135 3.3 3.465 V
Output Supply Voltage VDDIO Supply voltage for DIF outputs, if present 0.95 1.05 3.465 V
Commmercial range (T
COM
)0 70°C
Industrial range (T
IN
D
) -40 85 °C
Input High Voltage V
IH
Single-ended inputs, except SMBus, tri-level
inputs
2V
DD
+ 0.3 V
Input Low Voltage V
IL
Single-ended inputs, except SMBus, tri-level
inputs
GND
- 0.3 0.8 V
Input High Voltage V
IHTRI
Tri-Level Inputs 2.2 V
DD
+ 0.3 V
Input Mid Voltage V
IMTRI
Tri-Level Inputs 1.2 VDD/2 1.8 V
Input Low Voltage V
ILTRI
Tri-Level Inputs GND
- 0.3 0.8 V
I
IN
Single-ended inputs, V
IN
= GND, V
IN
= VDD -5 5 uA
I
INP
Single-ended inputs
V
IN
= 0 V; Inputs with internal pull-up resistors
V
IN
= VDD; Inputs with internal pull-down resistors
-200 200 uA
F
ib
yp
V
D
D
= 3.3 V, Bypass mode 33 150 MHz
F
i
p
ll
V
DD
= 3.3 V, 100MHz PLL mode 90 100.00 110 MHz
F
i
p
ll
V
DD
= 3.3 V, 133.33MHz PLL mode 120 133.33 147 MHz
Pin Inductance L
p
in
7nH1
C
IN
Logic Inputs, except DIF_IN 1.5 5 pF 1
C
INDIF_IN
DIF_IN differential clock inputs 1.5 2.7 pF 1,4
C
OUT
Output pin capacitance 6 pF 1
Clk Stabilization T
STAB
From V
DD
Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
0.18 1.8 ms 1,2
Input SS Modulation
Frequency PCIe
f
MODI NPCI e
Allowable Frequency for PCIe Applications
(Triangular Modulation)
30 33 kHz
OE# Latency t
LATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
4 10 clocks 1,2,3
Tdrive_PD# t
DRVPD
DIF output enable after
PD# de-assertion
300 us 1,3
Tfall t
F
Fall time of control inputs 5 ns 2
Trise t
R
Rise time of control inputs 5 ns 2
1
Guaranteed by design and characterization, not 100% tested in production.
2
Control input must be monotonic from 20% to 80% of input swing.
Capacitance
3
Time from deassertion until out
p
uts are >200 mV
4
DIF_IN input
Ambient Operating
Temperature
T
AMB
Input Current
Input Frequency
12-OUTPUT DB1200ZL 8 REVISION J 05/25/16
9ZXL1231 DATASHEET
Electrical Characteristics–DIF Low Power HCSL Outputs
Electrical Characteristics–Current Consumption
T
AMB
= T
COM
or T
IND
, unless noted., Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
T
AMB
= T
COM
, Scope averaging on 1.5 3.3 4
V/ns
1,2,3
T
AMB
= T
IND
Scope averaging on 1.5 3.1 4.5
V/ns
1,2,3
Slew rate matching
Δ
dV/dt Slew rate matching, Scope averaging on 7 20
%
1,2,4
Voltage High VHigh 660 778 850
Voltage Low VLow -150 0 150
Max Voltage Vmax 868 1150
Min Voltage Vmin -300 -64
Crossing Voltage (abs) Vcross_abs Scope averaging off 250 430 550 mV 1,5
Crossing Voltage (var)
Δ
-Vcross Scope averaging off 17 140 mV 1,6
2
Measured from differential waveform
7
At default SMBus settin
g
s.
Slew rate dV/dt
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope
averaging on)
mV
Measurement on single ended signal using
absolute value. (Scope averaging off)
mV
1
Guaranteed by design and characterization, not 100% tested in production.
3
Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5
Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
6
The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross
absolute) allowed. The intent is to limit Vcross induced modulation by setting
Δ
-Vcross to be smaller than Vcross absolute.
T
AMB
= T
COM
or T
IND
, unless noted., Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
VDDA, PLL Mode@100MHz 18 20 mA 1
VDDA, PLL Bypass Mode@100MHz 6 10 mA 1
I
D
D
All other VDD pins 16 25 mA
I
DDIO
VDDIO for DIF outputs, if applicable 91 110 mA
VDDA, PLL Mode@100MHz 3 5 mA 1
VDDA, PLL Bypass Mode@100MHz 3 5 mA 1
I
D
D
All other VDD pins 0.01 1 mA
I
DDIO
VDDIO for DIF outputs, if applicable 0.01 0.3 mA
1.
Includes VDDR if applicable
Operating Supply Current
I
DDA
Power Down Current
I
DDA
REVISION J 05/25/16 9 12-OUTPUT DB1200ZL
9ZXL1231 DATASHEET
Electrical Characteristics–Skew and Differential Jitter Parameters
T
AMB
= T
COM
or T
IND
, unless noted., Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
CLK_IN, DIF[x:0] t
SPO_PLL
Input-to-Output Skew in PLL mode
@ nominal temperature and voltage
-100 -60 100 ps 1,2,4,5,8
CLK_IN, DIF[x:0] t
PD_BYP
Input-to-Output Skew in Bypass mode
@ nominal temperature and voltage
2.5 3.6 4.5 ns 1,2,3,5,8
CLK_IN, DIF[x:0] t
DSPO_PLL
Input-to-Output Skew Varation in PLL mode
across voltage and temperature
-50 0 50 ps 1,2,3,5,8
Input-to-Output Skew Varation in Bypass mode
T
AMB
= T
COM
-250 250 ps 1,2,3,5,8
Input-to-Output Skew Varation in Bypass mode
T
AMB
= T
IND
-350 350 ps 1,2,3,5,8
Output-to-Output Skew across all outputs
@100MHz, T
AMB
= T
COM
30 50 ps 1,2,3,8
Output-to-Output Skew across all outputs @
100MHz, T
AMB
= T
IND
30 65 ps 1,2,3,8
PLL Jitter Peaking j
p
eak-hibw
LOBW#_BYPASS_HIBW = 1 0 1.2 2.5 dB 7,8
PLL Jitter Peaking j
p
eak-lobw
LOBW#_BYPASS_HIBW = 0 0 0.8 2 dB 7,8
PLL Bandwidth pll
HIBW
LOBW#_BYPASS_HIBW = 1 234MHz 8,9
PLL Bandwidth pll
LOBW
LOBW#_BYPASS_HIBW = 0 0.7 1.1 1.4 MHz 8,9
Duty Cycle t
DC
Measured differentially, PLL Mode 45 50 55 % 1
Duty Cycle Distortion t
DCD
Measured differentially, Bypass Mode
@100MHz
-1.5 -0.6 0 % 1,10
PLL mode 34 50 ps 1,11
Additive Jitter in Bypass Mode 1 5 ps 1,11
Notes for preceding table:
6.
t is the period of the input clock
7
Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking.
8.
Guaranteed by desi
g
n and characterization, not 100% tested in production.
9
Measured at 3 db down or half power point.
10
Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mo
d
11
Measured from differential waveform
3
All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.
4
This parameter is deterministic for a given device
DIF{x:0] t
SKEW_ALL
t
DSPO_BYP
CLK_IN, DIF[x:0]
5
Measured with scope averaging on to find mean value.
Jitter, Cycle to cycle t
jcyc-cyc
1
Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input.
2
Measured from differential cross-point to differential cross-point. This parameter can be tuned with external feedback path, if present.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

9ZXL1231AKLF

Mfr. #:
Buy 9ZXL1231AKLF
Manufacturer:
IDT
Description:
Clock Buffer HIGH PERF. ZDB - LOW POWER
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