MT88E39 Data Sheet
10
Zarlink Semiconductor Inc.
Electrical characteristics are over recommended operating conditions, unless otherwise stated.
Typical figures are at 25
°C and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics are over recommended operating conditions, unless otherwise stated.
Typical figures are at 25
°C and are for design aid only: not guaranteed and not subject to production testing.
Notes*:
1. dBm = Decibels above or below a reference power of 1 mW into 600 Ω. 0 dBm = 0.7746 Vrms.
2. dBV = Decibels above or below a reference voltage of 1 Vrms. 0 dBV = 1 Vrms.
3. Input op-amp configured to 0 dB gain at Vdd = 5 V+/-10%, -3 dB at Vdd = 3 V+/-10%.
4. Mark and Space frequencies have the same amplitude.
5. Band limited random noise (200-3400 Hz). Present when FSK signal present.
6. OSC1 at 3.579545 MHz
±0.2%.
Electrical Characteristics
- Gain Setting Amplifier
Characteristics Sym. Min. Typ.
Max. Units Test Conditions
1 Input Leakage Current I
IN
1 µAV
SS
V
IN
V
DD
2 Input Resistance R
in
5M
3 Input Offset Voltage V
OS
25 mV
4 Power Supply Rejection Ratio PSRR 30 dB 1 kHz ripple on V
DD
5 Common Mode Rejection CMRR 30 dB V
CMmin
V
IN
V
CMmax
6 DC Open Loop Voltage Gain A
VOL
40 dB
7 Unity Gain Bandwidth f
C
0.2 MHz
8 Output Voltage Swing V
O
0.5
V
DD
-0.7
V Load 100 k
9 Capacitive Load (GS) C
L
50 pF
10 Resistive Load (GS) R
L
100 k
11 Common Mode Voltage Range V
CM
1.0
V
DD
-1.0
V
AC Electrical Characteristics
- FSK
Characteristics Sym. Min. Typ.
Max. Units Notes*
1 Input Detection Level -37.78
-40
10
-1.78
-4
631
dBm
dBV
mVrms
1, 2, 3, 4
2 Input Baud Rate 1188 1200 1212 baud 6
3 Input Frequency Detection
Bell 202 1 (Mark)
Bell 202 0 (Space)
CCITT V.23 1 (Mark)
CCITT V.23 0 (Space)
1188
2178
1280.5
2068.5
1200
2200
1300
2100
1212
2222
1319.5
2131.5
Hz
Hz
Hz
Hz
4 Input Noise Tolerance
20 log SNR 20 dB 3, 4, 5
5Twist=
20 log -6 10 dB
V
Mark
V
Space
()
MT88E39 Data Sheet
11
Zarlink Semiconductor Inc.
AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.
Typical figures are at 25
°C and are for design aid only, not guaranteed and not subject to production testing.
Notes*:
1. The device will stop functioning within this time, but more time may be required to reach I
DDQ
.
AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.
Typical figures are at 25
°C and are for design aid only, not guaranteed and not subject to production testing.
Notes*:
1. FSK input data at 1200
±12 baud.
2. OSC1 at 3.579545 MHz
±0.2%.
3. 10 k to V
SS
, 50pF to V
SS.
4. 10 k to V
DD
, 50pF to V
SS
.
5. Function of signal condition.
6. For a repeating mark space sequence, the data stream will typically have equal 1 and 0 bit durations.
AC Electrical Characteristics
- Timing
Characteristics Sym. Min. Typ.
Max. Units Notes*
1
PWDN
OSC1
Power-up time t
PU
50 ms
2 Power-down time t
PD
100 1000 µs1
3
CD
Input FSK to CD low delay t
IAL
25 ms
4 Input FSK to CD
high delay t
IAH
10 ms
5Hysteresis 10 ms
AC Electrical Characteristics
- 3-Wire FSK Interface Timing (Mode 0)
Characteristics Sym. Min. Typ.
Max. Units. Notes*
1
DATA
Rate 1188 1200 1212 bps 1, 6
2 Input FSK to DATA delay t
IDD
15ms
3
DATA
DCLK
Rise time t
R
200 ns 3
4 Fall time t
F
200 ns 3
5 DATA to DCLK delay t
DCD
6416 µs 1, 2, 5, 6
6 DCLK to DATA delay t
CDD
6416 µs 1, 2, 5, 6
7
DCLK
Frequency 1200.4 1202.8 1205.2 Hz 2
8 High time t
CH
415 416 417 µs2
9 Low time t
CL
415 416 417 µs2
10
DCLK
DR
DCLK to DR delay t
CRD
415 416 417 µs2
11
DR
Rise time t
RR
10 µs4
12 Fall time t
FF
200 ns 4
13 Low time t
RL
415 416 417 µs2
MT88E39 Data Sheet
12
Zarlink Semiconductor Inc.
AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.
Typical figures are at 25
°C and are for design aid only, not guaranteed and not subject to production testing.
Figure 8 - DATA and DCLK Output Timing (Mode 0)
Figure 9 - DR
Output Timing (Mode 0)
AC Electrical Characteristics
- 3-Wire FSK Interface Timing (Mode 1)
Characteristics Sym. Min. Typ.
Max. Units Notes*
1
DCLK
Frequency f
DCLK1
1 MHz See Fig. 12
2Duty Cycle 30 70%
3Rise Time 100ns
4
DCLK
DR
DCLK low setup time to DR t
DDS
500 ns See Fig. 12
5 DCLK low hold time to DR
t
DDH
500 ns See Fig. 12
DATA
DCLK
t
R
t
DCD
t
CDD
t
R
t
F
t
CL
t
CH
t
F
t
FF
t
RR
t
RL
DR

MT88E39AS1

Mfr. #:
Manufacturer:
Microchip / Microsemi
Description:
Telecom Interface ICs Pb Free CNIC 1.1
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet